[llvm] 2ff226a - MCAsmBackend,Hexagon: Remove MCRelaxableFragment from fixupNeedsRelaxationAdvanced
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 13 21:45:33 PDT 2025
Author: Fangrui Song
Date: 2025-04-13T21:45:29-07:00
New Revision: 2ff226ae2c9bdafc686d698b69b4a8519213f325
URL: https://github.com/llvm/llvm-project/commit/2ff226ae2c9bdafc686d698b69b4a8519213f325
DIFF: https://github.com/llvm/llvm-project/commit/2ff226ae2c9bdafc686d698b69b4a8519213f325.diff
LOG: MCAsmBackend,Hexagon: Remove MCRelaxableFragment from fixupNeedsRelaxationAdvanced
Among fixupNeedsRelaxationAdvanced (introduced by
https://reviews.llvm.org/D8217) targets, only Hexagon needs the
`MCRelaxableFragment` parameter (commit
86f218e7ec5d941b7785eaebcb8f4cad76db8a64) to get the instruction packet
(MCInst with sub-instruction operands).
As fixupNeedsRelaxationAdvanced follows mayNeedRelaxation, we can store
the MCInst in mayNeedRelaxation and eliminate the MCRelaxableFragment
parameter.
Follow-up to 7c83b7ef1796210451b839f4c58f2815f4aedfe5 that eliminates
the MCRelaxableFragment parameter from fixupNeedsRelaxation.
Added:
Modified:
llvm/include/llvm/MC/MCAsmBackend.h
llvm/lib/MC/MCAsmBackend.cpp
llvm/lib/MC/MCAssembler.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCAsmBackend.h b/llvm/include/llvm/MC/MCAsmBackend.h
index 1c9feef10a337..10eabd41e80fc 100644
--- a/llvm/include/llvm/MC/MCAsmBackend.h
+++ b/llvm/include/llvm/MC/MCAsmBackend.h
@@ -153,7 +153,6 @@ class MCAsmBackend {
/// Target specific predicate for whether a given fixup requires the
/// associated instruction to be relaxed.
virtual bool fixupNeedsRelaxationAdvanced(const MCAssembler &,
- const MCRelaxableFragment &,
const MCFixup &, const MCValue &,
uint64_t, bool Resolved) const;
diff --git a/llvm/lib/MC/MCAsmBackend.cpp b/llvm/lib/MC/MCAsmBackend.cpp
index f6113e62c0360..85a208ffbce0a 100644
--- a/llvm/lib/MC/MCAsmBackend.cpp
+++ b/llvm/lib/MC/MCAsmBackend.cpp
@@ -116,7 +116,6 @@ bool MCAsmBackend::shouldForceRelocation(const MCAssembler &, const MCFixup &,
}
bool MCAsmBackend::fixupNeedsRelaxationAdvanced(const MCAssembler &,
- const MCRelaxableFragment &,
const MCFixup &Fixup,
const MCValue &, uint64_t Value,
bool Resolved) const {
diff --git a/llvm/lib/MC/MCAssembler.cpp b/llvm/lib/MC/MCAssembler.cpp
index 69803f0a2ed55..4e925809d20b0 100644
--- a/llvm/lib/MC/MCAssembler.cpp
+++ b/llvm/lib/MC/MCAssembler.cpp
@@ -999,8 +999,8 @@ bool MCAssembler::fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value;
bool Resolved = evaluateFixup(Fixup, DF, Target, DF->getSubtargetInfo(),
Value, /*RecordReloc=*/false);
- return getBackend().fixupNeedsRelaxationAdvanced(*this, *DF, Fixup, Target,
- Value, Resolved);
+ return getBackend().fixupNeedsRelaxationAdvanced(*this, Fixup, Target, Value,
+ Resolved);
}
bool MCAssembler::fragmentNeedsRelaxation(const MCRelaxableFragment *F) const {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index ff04d88db4fec..88bcf4cc9c6c6 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -354,9 +354,11 @@ static bool needsInterworking(const MCAssembler &Asm, const MCSymbol *Sym,
return false;
}
-bool ARMAsmBackend::fixupNeedsRelaxationAdvanced(
- const MCAssembler &Asm, const MCRelaxableFragment &, const MCFixup &Fixup,
- const MCValue &Target, uint64_t Value, bool Resolved) const {
+bool ARMAsmBackend::fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,
+ const MCFixup &Fixup,
+ const MCValue &Target,
+ uint64_t Value,
+ bool Resolved) const {
const MCSymbol *Sym = Target.getAddSym();
if (needsInterworking(Asm, Sym, Fixup.getTargetKind()))
return true;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
index df2d375ac32b8..57588d989d545 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
@@ -55,7 +55,6 @@ class ARMAsmBackend : public MCAsmBackend {
uint64_t Value) const;
bool fixupNeedsRelaxationAdvanced(const MCAssembler &,
- const MCRelaxableFragment &,
const MCFixup &, const MCValue &, uint64_t,
bool) const override;
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
index 4643b6a811ad0..792a55555a0d0 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
@@ -171,9 +171,11 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
}
}
-bool CSKYAsmBackend::fixupNeedsRelaxationAdvanced(
- const MCAssembler &, const MCRelaxableFragment &, const MCFixup &Fixup,
- const MCValue &, uint64_t Value, bool Resolved) const {
+bool CSKYAsmBackend::fixupNeedsRelaxationAdvanced(const MCAssembler &,
+ const MCFixup &Fixup,
+ const MCValue &,
+ uint64_t Value,
+ bool Resolved) const {
// Return true if the symbol is unresolved.
if (!Resolved)
return true;
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
index f8201dc57c2b8..3ce2f37212dca 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
@@ -40,7 +40,6 @@ class CSKYAsmBackend : public MCAsmBackend {
const MCSubtargetInfo &STI) const override;
bool fixupNeedsRelaxationAdvanced(const MCAssembler &,
- const MCRelaxableFragment &,
const MCFixup &, const MCValue &, uint64_t,
bool) const override;
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index c37953bc68a31..ae1dac57d9294 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -41,6 +41,7 @@ class HexagonAsmBackend : public MCAsmBackend {
uint8_t OSABI;
StringRef CPU;
mutable uint64_t relaxedCnt;
+ mutable const MCInst *RelaxedMCB = nullptr;
std::unique_ptr <MCInstrInfo> MCII;
std::unique_ptr <MCInst *> RelaxTarget;
MCInst * Extender;
@@ -560,17 +561,17 @@ class HexagonAsmBackend : public MCAsmBackend {
/// \param Inst - The instruction to test.
bool mayNeedRelaxation(MCInst const &Inst,
const MCSubtargetInfo &STI) const override {
+ RelaxedMCB = &Inst;
return true;
}
/// fixupNeedsRelaxation - Target specific predicate for whether a given
/// fixup requires the associated instruction to be relaxed.
bool fixupNeedsRelaxationAdvanced(const MCAssembler &Asm,
- const MCRelaxableFragment &DF,
const MCFixup &Fixup, const MCValue &,
uint64_t Value,
bool Resolved) const override {
- MCInst const &MCB = DF.getInst();
+ MCInst const &MCB = *RelaxedMCB;
assert(HexagonMCInstrInfo::isBundle(MCB));
*RelaxTarget = nullptr;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
index 410767fc3b468..b36b8bd3fb436 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
@@ -141,9 +141,11 @@ bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
return STI->hasFeature(RISCV::FeatureRelax) || ForceRelocs;
}
-bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(
- const MCAssembler &, const MCRelaxableFragment &, const MCFixup &Fixup,
- const MCValue &, uint64_t Value, bool Resolved) const {
+bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCAssembler &,
+ const MCFixup &Fixup,
+ const MCValue &,
+ uint64_t Value,
+ bool Resolved) const {
if (!RelaxBranches)
return false;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
index 32d6128ba7182..5d585b4efc116 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
@@ -69,7 +69,6 @@ class RISCVAsmBackend : public MCAsmBackend {
const MCSubtargetInfo *STI) override;
bool fixupNeedsRelaxationAdvanced(const MCAssembler &,
- const MCRelaxableFragment &,
const MCFixup &, const MCValue &, uint64_t,
bool) const override;
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index 09b8dba1b025c..cb23487e6fbe0 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -178,7 +178,6 @@ class X86AsmBackend : public MCAsmBackend {
const MCSubtargetInfo &STI) const override;
bool fixupNeedsRelaxationAdvanced(const MCAssembler &,
- const MCRelaxableFragment &,
const MCFixup &, const MCValue &, uint64_t,
bool) const override;
@@ -730,9 +729,11 @@ bool X86AsmBackend::mayNeedRelaxation(const MCInst &MI,
MI.getOperand(MI.getNumOperands() - 1 - SkipOperands).isExpr());
}
-bool X86AsmBackend::fixupNeedsRelaxationAdvanced(
- const MCAssembler &, const MCRelaxableFragment &, const MCFixup &Fixup,
- const MCValue &Target, uint64_t Value, bool Resolved) const {
+bool X86AsmBackend::fixupNeedsRelaxationAdvanced(const MCAssembler &,
+ const MCFixup &Fixup,
+ const MCValue &Target,
+ uint64_t Value,
+ bool Resolved) const {
// If resolved, relax if the value is too big for a (signed) i8.
//
// Currently, `jmp local at plt` relaxes JMP even if the offset is small,
More information about the llvm-commits
mailing list