[llvm] [AMDGPU] Switch V_CNDMASK operands to shrink it into VOP2 (PR #135162)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,121 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GCN
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefix=GCN
+
+define amdgpu_cs void @test_u32(i32 %a, i32 %x, i32 %y, i32 %p, i32 %q, i32 %r, i32 %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT:    v_dual_cndmask_b32 v0, v1, v2 :: v_dual_cndmask_b32 v1, 0, v3
+; GCN-NEXT:    v_dual_cndmask_b32 v2, 0, v4 :: v_dual_cndmask_b32 v3, v5, v6
+; GCN-NEXT:    global_store_b128 v[7:8], v[0:3], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = icmp eq i32 %a, -1
+  %val1 = select i1 %vcc, i32 %x, i32 %y
+  %val2 = select i1 %vcc, i32 0, i32 %p
+  %val3 = select i1 %vcc, i32 0, i32 %q
+  %val4 = select i1 %vcc, i32 %r, i32 %s
+  %ret0 = insertelement <4 x i32> poison, i32 %val1, i32 0
+  %ret1 = insertelement <4 x i32> %ret0, i32 %val2, i32 1
+  %ret2 = insertelement <4 x i32> %ret1, i32 %val3, i32 2
+  %ret3 = insertelement <4 x i32> %ret2, i32 %val4, i32 3
+  store <4 x i32> %ret3, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_cs void @test_u32_negative_case(i32 %a, i32 %x, i32 %y, i32 %p, i32 %q, i32 %r, i32 %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u32_negative_case:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc_lo, -1, v0
+; GCN-NEXT:    v_dual_cndmask_b32 v0, v1, v2 :: v_dual_cndmask_b32 v1, 0, v3
+; GCN-NEXT:    v_dual_cndmask_b32 v2, 0, v4 :: v_dual_cndmask_b32 v3, v5, v6
+; GCN-NEXT:    global_store_b128 v[7:8], v[0:3], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = icmp eq i32 %a, -1
+  %val1 = select i1 %vcc, i32 %x, i32 %y
+  %val2 = select i1 %vcc, i32 0, i32 %p
+  %val3 = select i1 %vcc, i32 0, i32 %q
+  %val4 = select i1 %vcc, i32 %r, i32 %s
+  %ret0 = insertelement <4 x i32> poison, i32 %val1, i32 0
+  %ret1 = insertelement <4 x i32> %ret0, i32 %val2, i32 1
+  %ret2 = insertelement <4 x i32> %ret1, i32 %val3, i32 2
+  %ret3 = insertelement <4 x i32> %ret2, i32 %val4, i32 3
+  store <4 x i32> %ret3, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_cs void @test_u64(i64 %a, i64 %x, i64 %y, i64 %p, i64 %q, i64 %r, i64 %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_u64:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_ne_u64_e32 vcc_lo, -1, v[0:1]
+; GCN-NEXT:    v_dual_cndmask_b32 v1, v3, v5 :: v_dual_cndmask_b32 v0, v2, v4
+; GCN-NEXT:    v_dual_cndmask_b32 v3, 0, v7 :: v_dual_cndmask_b32 v8, 0, v8
+; GCN-NEXT:    v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v10, v10, v12
+; GCN-NEXT:    v_dual_cndmask_b32 v11, v11, v13 :: v_dual_cndmask_b32 v2, 0, v6
+; GCN-NEXT:    s_clause 0x1
+; GCN-NEXT:    global_store_b128 v[14:15], v[8:11], off offset:16
+; GCN-NEXT:    global_store_b128 v[14:15], v[0:3], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = icmp eq i64 %a, -1
+  %val1 = select i1 %vcc, i64 %x, i64 %y
+  %val2 = select i1 %vcc, i64 0, i64 %p
+  %val3 = select i1 %vcc, i64 0, i64 %q
+  %val4 = select i1 %vcc, i64 %r, i64 %s
+  %ret0 = insertelement <4 x i64> poison, i64 %val1, i32 0
+  %ret1 = insertelement <4 x i64> %ret0, i64 %val2, i32 1
+  %ret2 = insertelement <4 x i64> %ret1, i64 %val3, i32 2
+  %ret3 = insertelement <4 x i64> %ret2, i64 %val4, i32 3
+  store <4 x i64> %ret3, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_cs void @test_f32(float %a, float %x, float %y, float %p, float %q, float %r, float %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f32:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_neq_f32_e32 vcc_lo, 1.0, v0
+; GCN-NEXT:    v_dual_cndmask_b32 v0, v1, v2 :: v_dual_cndmask_b32 v1, 0, v3
+; GCN-NEXT:    v_dual_cndmask_b32 v2, 0, v4 :: v_dual_cndmask_b32 v3, v5, v6
+; GCN-NEXT:    global_store_b128 v[7:8], v[0:3], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = fcmp oeq float %a, 1.0
+  %val1 = select i1 %vcc, float %x, float %y
+  %val2 = select i1 %vcc, float 0.0, float %p
+  %val3 = select i1 %vcc, float 0.0, float %q
+  %val4 = select i1 %vcc, float %r, float %s
+  %ret0 = insertelement <4 x float> poison, float %val1, i32 0
+  %ret1 = insertelement <4 x float> %ret0, float %val2, i32 1
+  %ret2 = insertelement <4 x float> %ret1, float %val3, i32 2
+  %ret3 = insertelement <4 x float> %ret2, float %val4, i32 3
+  store <4 x float> %ret3, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_cs void @test_f64(double %a, double %x, double %y, double %p, double %q, double %r, double %s, ptr addrspace(1) %out) {
+; GCN-LABEL: test_f64:
+; GCN:       ; %bb.0: ; %.entry
+; GCN-NEXT:    v_cmp_neq_f64_e32 vcc_lo, 1.0, v[0:1]
+; GCN-NEXT:    v_dual_cndmask_b32 v1, v3, v5 :: v_dual_cndmask_b32 v0, v2, v4
+; GCN-NEXT:    v_dual_cndmask_b32 v3, 0, v7 :: v_dual_cndmask_b32 v8, 0, v8
+; GCN-NEXT:    v_dual_cndmask_b32 v9, 0, v9 :: v_dual_cndmask_b32 v10, v10, v12
+; GCN-NEXT:    v_dual_cndmask_b32 v11, v11, v13 :: v_dual_cndmask_b32 v2, 0, v6
+; GCN-NEXT:    s_clause 0x1
+; GCN-NEXT:    global_store_b128 v[14:15], v[8:11], off offset:16
+; GCN-NEXT:    global_store_b128 v[14:15], v[0:3], off
+; GCN-NEXT:    s_endpgm
+.entry:
+  %vcc = fcmp oeq double %a, 1.0
----------------
arsenm wrote:

Test all the compare kinds. Can you get this to one pair per test? 

https://github.com/llvm/llvm-project/pull/135162