[llvm] [RISCV][MC] Emit `x8` as `fp` instead of `s0` (PR #135500)

[Sam Elliott via llvm-commits]

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@@ -311,6 +315,8 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
 }
 
 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
+  if (EmitX8AsFP && Reg == RISCV::X8)
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lenary wrote:

There are quite a few registers that are written as `x8`/`s0` - `X8`, but also `X8_H`, `X8_W`, and `X8_X9`. It would be good if there's a comment to say why those ones aren't printed as `fp` (I think it's fine they're not, as the first two denote f16/f32 registers, and the latter is a GPR pair, none of which are quite the same as a frame pointer).

https://github.com/llvm/llvm-project/pull/135500