[llvm] [RISCV][MC] Emit `x8` as `fp` instead of `s0` (PR #135500)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Shao-Ce SUN (sunshaoce)

<details>
<summary>Changes</summary>

I think sometimes, when emphasizing `X8`'s functionality related to Frame Pointer, this option can be passed.

---
Full diff: https://github.com/llvm/llvm-project/pull/135500.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+6) 
- (added) llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll (+49) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 83ecf805489c1..8693bda718d91 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -34,6 +34,10 @@ static cl::opt<bool>
               cl::desc("Disable the emission of assembler pseudo instructions"),
               cl::init(false), cl::Hidden);
 
+static cl::opt<bool> EmitX8AsFP("riscv-emit-x8-as-fp",
+                                cl::desc("Emit x8 as fp instead of s0"),
+                                cl::init(false), cl::Hidden);
+
 // Print architectural register names rather than the ABI names (such as x2
 // instead of sp).
 // TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
@@ -311,6 +315,8 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
 }
 
 const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
+  if (EmitX8AsFP && Reg == RISCV::X8)
+    return "fp";
   return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName
                                            : RISCV::ABIRegAltName);
 }
diff --git a/llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll b/llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
new file mode 100644
index 0000000000000..773b49e3515ca
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 --riscv-emit-x8-as-fp -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv64 --riscv-emit-x8-as-fp -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
+
+define signext i32 @add(i32 %0, i32 %1) #0 {
+; RV32I-LABEL: add:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw fp, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    addi fp, sp, 16
+; RV32I-NEXT:    sw a0, -12(fp)
+; RV32I-NEXT:    sw a1, -16(fp)
+; RV32I-NEXT:    lw a0, -12(fp)
+; RV32I-NEXT:    lw a1, -16(fp)
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw fp, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: add:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi sp, sp, -32
+; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    sd fp, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT:    addi fp, sp, 32
+; RV64I-NEXT:    sw a0, -20(fp)
+; RV64I-NEXT:    sw a1, -24(fp)
+; RV64I-NEXT:    lw a0, -20(fp)
+; RV64I-NEXT:    lw a1, -24(fp)
+; RV64I-NEXT:    addw a0, a0, a1
+; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    ld fp, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    ret
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  store i32 %0, ptr %3, align 4
+  store i32 %1, ptr %4, align 4
+  %5 = load i32, ptr %3, align 4
+  %6 = load i32, ptr %4, align 4
+  %7 = add nsw i32 %5, %6
+  ret i32 %7
+}
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" }

``````````

</details>


https://github.com/llvm/llvm-project/pull/135500