[llvm] [AMDGPU] Switch V_CNDMASK operands to shrink it into VOP2 (PR #135162)

[Mirko Brkušanin via llvm-commits]

================
@@ -851,92 +851,137 @@ unsigned SIShrinkInstructions::getInverseCompareOpcode(MachineInstr &MI) const {
     return AMDGPU::V_CMP_LE_U32_e64;
   case AMDGPU::V_CMP_LT_U32_e64:
     return AMDGPU::V_CMP_GE_U32_e64;
-    // float 32
+    // unsigned 64
+  case AMDGPU::V_CMP_EQ_U64_e64:
+    return AMDGPU::V_CMP_NE_U64_e64;
+  case AMDGPU::V_CMP_NE_U64_e64:
+    return AMDGPU::V_CMP_EQ_U64_e64;
+  case AMDGPU::V_CMP_GE_U64_e64:
+    return AMDGPU::V_CMP_LT_U64_e64;
+  case AMDGPU::V_CMP_LE_U64_e64:
+    return AMDGPU::V_CMP_GT_U64_e64;
+  case AMDGPU::V_CMP_GT_U64_e64:
+    return AMDGPU::V_CMP_LE_U64_e64;
+  case AMDGPU::V_CMP_LT_U64_e64:
+    return AMDGPU::V_CMP_GE_U64_e64;
+  // float 32
   case AMDGPU::V_CMP_EQ_F32_e64:
     return AMDGPU::V_CMP_NEQ_F32_e64;
   case AMDGPU::V_CMP_NEQ_F32_e64:
     return AMDGPU::V_CMP_EQ_F32_e64;
   case AMDGPU::V_CMP_GE_F32_e64:
-    return AMDGPU::V_CMP_LT_F32_e64;
+    return AMDGPU::V_CMP_NGE_F32_e64;
   case AMDGPU::V_CMP_LE_F32_e64:
-    return AMDGPU::V_CMP_GT_F32_e64;
+    return AMDGPU::V_CMP_NLE_F32_e64;
   case AMDGPU::V_CMP_GT_F32_e64:
-    return AMDGPU::V_CMP_LE_F32_e64;
+    return AMDGPU::V_CMP_NGT_F32_e64;
   case AMDGPU::V_CMP_LT_F32_e64:
-    return AMDGPU::V_CMP_GE_F32_e64;
+    return AMDGPU::V_CMP_NLT_F32_e64;
+  // float 64
+  case AMDGPU::V_CMP_EQ_F64_e64:
+    return AMDGPU::V_CMP_NEQ_F64_e64;
+  case AMDGPU::V_CMP_NEQ_F64_e64:
+    return AMDGPU::V_CMP_EQ_F64_e64;
+  case AMDGPU::V_CMP_GE_F64_e64:
+    return AMDGPU::V_CMP_NGE_F64_e64;
+  case AMDGPU::V_CMP_LE_F64_e64:
+    return AMDGPU::V_CMP_NLE_F64_e64;
+  case AMDGPU::V_CMP_GT_F64_e64:
+    return AMDGPU::V_CMP_NGT_F64_e64;
+  case AMDGPU::V_CMP_LT_F64_e64:
+    return AMDGPU::V_CMP_NLT_F64_e64;
   default:
     return 0;
   }
 }
 
-bool SIShrinkInstructions::shouldSwitchOperands(MachineRegisterInfo &MRI,
-                                                MachineInstr &MI,
-                                                const SIInstrInfo &TII) const {
-  auto allUses = MRI.use_nodbg_operands(MI.getOperand(5).getReg());
-  unsigned Count = 0;
+bool SIShrinkInstructions::shouldSwapCndOperands(
+    MachineInstr &MI, const SIInstrInfo &TII,
+    SmallVector<MachineOperand *, 4> &UsesToProcess) const {
+  auto AllUses = MRI->use_nodbg_operands(MI.getOperand(0).getReg());
+  bool ShouldSwap = false;
 
-  for (auto &Use : allUses) {
-    if (Use.getParent()->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
+  for (auto &Use : AllUses) {
+    MachineInstr *UseInst = Use.getParent();
+    if (UseInst->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
       return false;
-    MachineOperand *Src0 =
-        TII.getNamedOperand(*Use.getParent(), AMDGPU::OpName::src0);
-    MachineOperand *Src1 =
-        TII.getNamedOperand(*Use.getParent(), AMDGPU::OpName::src1);
+    MachineOperand *Src0 = TII.getNamedOperand(*UseInst, AMDGPU::OpName::src0);
+    MachineOperand *Src1 = TII.getNamedOperand(*UseInst, AMDGPU::OpName::src1);
----------------
mbrkusanin wrote:

These are just MI.getOperand(2) and MI.getOperand(4). No need to use getNamedOperand.

https://github.com/llvm/llvm-project/pull/135162