[llvm] a4b7688 - [AArch64] Regenerate fsh.ll test. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 11 08:37:46 PDT 2025
Author: David Green
Date: 2025-04-11T16:37:42+01:00
New Revision: a4b7688d27da1a0189fff6549853fdfe22b33c48
URL: https://github.com/llvm/llvm-project/commit/a4b7688d27da1a0189fff6549853fdfe22b33c48
DIFF: https://github.com/llvm/llvm-project/commit/a4b7688d27da1a0189fff6549853fdfe22b33c48.diff
LOG: [AArch64] Regenerate fsh.ll test. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/fsh.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fsh.ll b/llvm/test/CodeGen/AArch64/fsh.ll
index c084813760b80..2cee2f2b2686c 100644
--- a/llvm/test/CodeGen/AArch64/fsh.ll
+++ b/llvm/test/CodeGen/AArch64/fsh.ll
@@ -3905,102 +3905,66 @@ entry:
}
define <8 x i8> @fshl_v8i8_c(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-SD-LABEL: fshl_v8i8_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.8b, v0.8b, #3
-; CHECK-SD-NEXT: usra v0.8b, v1.8b, #5
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshl_v8i8_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.8b, v0.8b, #3
-; CHECK-GI-NEXT: usra v0.8b, v1.8b, #5
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshl_v8i8_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.8b, v0.8b, #3
+; CHECK-NEXT: usra v0.8b, v1.8b, #5
+; CHECK-NEXT: ret
entry:
%d = call <8 x i8> @llvm.fshl(<8 x i8> %a, <8 x i8> %b, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <8 x i8> %d
}
define <8 x i8> @fshr_v8i8_c(<8 x i8> %a, <8 x i8> %b) {
-; CHECK-SD-LABEL: fshr_v8i8_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.8b, v0.8b, #5
-; CHECK-SD-NEXT: usra v0.8b, v1.8b, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshr_v8i8_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.8b, v0.8b, #5
-; CHECK-GI-NEXT: usra v0.8b, v1.8b, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshr_v8i8_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.8b, v0.8b, #5
+; CHECK-NEXT: usra v0.8b, v1.8b, #3
+; CHECK-NEXT: ret
entry:
%d = call <8 x i8> @llvm.fshr(<8 x i8> %a, <8 x i8> %b, <8 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <8 x i8> %d
}
define <16 x i8> @fshl_v16i8_c(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-SD-LABEL: fshl_v16i8_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.16b, v0.16b, #3
-; CHECK-SD-NEXT: usra v0.16b, v1.16b, #5
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshl_v16i8_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.16b, v0.16b, #3
-; CHECK-GI-NEXT: usra v0.16b, v1.16b, #5
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshl_v16i8_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.16b, v0.16b, #3
+; CHECK-NEXT: usra v0.16b, v1.16b, #5
+; CHECK-NEXT: ret
entry:
%d = call <16 x i8> @llvm.fshl(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %d
}
define <16 x i8> @fshr_v16i8_c(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-SD-LABEL: fshr_v16i8_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.16b, v0.16b, #5
-; CHECK-SD-NEXT: usra v0.16b, v1.16b, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshr_v16i8_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.16b, v0.16b, #5
-; CHECK-GI-NEXT: usra v0.16b, v1.16b, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshr_v16i8_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.16b, v0.16b, #5
+; CHECK-NEXT: usra v0.16b, v1.16b, #3
+; CHECK-NEXT: ret
entry:
%d = call <16 x i8> @llvm.fshr(<16 x i8> %a, <16 x i8> %b, <16 x i8> <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>)
ret <16 x i8> %d
}
define <4 x i16> @fshl_v4i16_c(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-SD-LABEL: fshl_v4i16_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.4h, v0.4h, #3
-; CHECK-SD-NEXT: usra v0.4h, v1.4h, #13
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshl_v4i16_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.4h, v0.4h, #3
-; CHECK-GI-NEXT: usra v0.4h, v1.4h, #13
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshl_v4i16_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.4h, v0.4h, #3
+; CHECK-NEXT: usra v0.4h, v1.4h, #13
+; CHECK-NEXT: ret
entry:
%d = call <4 x i16> @llvm.fshl(<4 x i16> %a, <4 x i16> %b, <4 x i16> <i16 3, i16 3, i16 3, i16 3>)
ret <4 x i16> %d
}
define <4 x i16> @fshr_v4i16_c(<4 x i16> %a, <4 x i16> %b) {
-; CHECK-SD-LABEL: fshr_v4i16_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.4h, v0.4h, #13
-; CHECK-SD-NEXT: usra v0.4h, v1.4h, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshr_v4i16_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.4h, v0.4h, #13
-; CHECK-GI-NEXT: usra v0.4h, v1.4h, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshr_v4i16_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.4h, v0.4h, #13
+; CHECK-NEXT: usra v0.4h, v1.4h, #3
+; CHECK-NEXT: ret
entry:
%d = call <4 x i16> @llvm.fshr(<4 x i16> %a, <4 x i16> %b, <4 x i16> <i16 3, i16 3, i16 3, i16 3>)
ret <4 x i16> %d
@@ -4087,34 +4051,22 @@ entry:
}
define <8 x i16> @fshl_v8i16_c(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-SD-LABEL: fshl_v8i16_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.8h, v0.8h, #3
-; CHECK-SD-NEXT: usra v0.8h, v1.8h, #13
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshl_v8i16_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #3
-; CHECK-GI-NEXT: usra v0.8h, v1.8h, #13
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshl_v8i16_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.8h, v0.8h, #3
+; CHECK-NEXT: usra v0.8h, v1.8h, #13
+; CHECK-NEXT: ret
entry:
%d = call <8 x i16> @llvm.fshl(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)
ret <8 x i16> %d
}
define <8 x i16> @fshr_v8i16_c(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-SD-LABEL: fshr_v8i16_c:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: shl v0.8h, v0.8h, #13
-; CHECK-SD-NEXT: usra v0.8h, v1.8h, #3
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: fshr_v8i16_c:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: shl v0.8h, v0.8h, #13
-; CHECK-GI-NEXT: usra v0.8h, v1.8h, #3
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: fshr_v8i16_c:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: shl v0.8h, v0.8h, #13
+; CHECK-NEXT: usra v0.8h, v1.8h, #3
+; CHECK-NEXT: ret
entry:
%d = call <8 x i16> @llvm.fshr(<8 x i16> %a, <8 x i16> %b, <8 x i16> <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>)
ret <8 x i16> %d
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