[llvm] [AMDGPU][GlobalISel] Enable kernel argument preloading (PR #134655)

[Shilei Tian via llvm-commits]

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@@ -497,6 +499,65 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
   // these from the dispatch pointer.
 }
 
+void AMDGPUCallLowering::lowerPreloadedParameter(
+    MachineIRBuilder &B, ArrayRef<Register> VRegs, Type *ArgTy,
+    uint64_t ArgOffset, Align Alignment,
+    ArrayRef<MCRegister> PreloadRegs) const {
+  MachineFunction &MF = B.getMF();
+  const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
+  MachineRegisterInfo &MRI = MF.getRegInfo();
+  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+  const DataLayout &DL = B.getDataLayout();
+
+  LLT ResTy = getLLTForType(*ArgTy, DL);
+  LLT ScalarTy = LLT::scalar(DL.getTypeSizeInBits(ArgTy));
+  unsigned TotalSize = 0;
+  SmallVector<Register> SrcRegs(PreloadRegs.size());
+
+  for (auto &&[Idx, PhysReg] : enumerate(PreloadRegs)) {
+    Register VReg = MRI.getLiveInVirtReg(PhysReg);
+    TypeSize RegSize = TRI->getRegSizeInBits(VReg, MRI);
+
+    if (!MRI.getVRegDef(VReg)) {
+      MRI.setType(VReg, LLT::scalar(RegSize));
+      B.getMBB().addLiveIn(PhysReg);
+      B.buildInstr(TargetOpcode::COPY).addDef(VReg).addReg(PhysReg);
+    }
+
+    if (DL.getTypeStoreSize(ArgTy) < 4 && Alignment < 4) {
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shiltian wrote:

I'd use a `constexr const unsigned` for the `4` here to make the intention more clear.

https://github.com/llvm/llvm-project/pull/134655