[llvm] [SPIRV] Support for extension SPV_INTEL_device_side_avc_motion_estimation (PR #135319)
VISHAKH PRAKASH via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 10 22:55:05 PDT 2025
https://github.com/VishMCW created https://github.com/llvm/llvm-project/pull/135319
- Support for the extension SPV_INTEL_device_side_avc_motion_estimation
- Config changes to support .cl filetype in test suite
>From 3caf6703c0c57ffbf8572867e3c07b06a8ab9269 Mon Sep 17 00:00:00 2001
From: VishMCW <vishakh.prakash at multicorewareinc.com>
Date: Fri, 11 Apr 2025 11:07:55 +0530
Subject: [PATCH] FEAT: - Support for the extension
SPV_INTEL_device_side_avc_motion_estimation - Config changes to support .cl
filetype in test suite
---
llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 433 +++++++++++++++++-
llvm/lib/Target/SPIRV/SPIRVBuiltins.h | 4 +
llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 275 +++++++++++
llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp | 5 +-
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp | 365 +++++++++++++++
llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h | 17 +
llvm/lib/Target/SPIRV/SPIRVIRMapping.h | 17 +
llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 231 +++++++++-
llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 31 ++
llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 5 +-
.../Target/SPIRV/SPIRVPrepareFunctions.cpp | 1 -
.../lib/Target/SPIRV/SPIRVSymbolicOperands.td | 7 +-
.../subgroup_avc_intel_generic.cl | 193 ++++++++
.../subgroup_avc_intel_not_builtin.ll | 42 ++
.../subgroup_avc_intel_types.ll | 101 ++++
.../subgroup_avc_intel_vme_image.cl | 146 ++++++
.../subgroup_avc_intel_wrappers.ll | 154 +++++++
llvm/test/lit.cfg.py | 2 +-
18 files changed, 2020 insertions(+), 9 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_vme_image.cl
create mode 100644 llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
index 16364ab30f280..d56f83b4b94a4 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp
@@ -97,6 +97,25 @@ struct IntelSubgroupsBuiltin {
#define GET_IntelSubgroupsBuiltins_DECL
#define GET_IntelSubgroupsBuiltins_IMPL
+struct IntelSubgroupAvcBuiltin {
+ StringRef Name;
+ uint32_t Opcode;
+ bool IsRef;
+ bool IsSic;
+ bool IsEvaluate;
+};
+
+#define GET_IntelSubgroupAvcBuiltins_DECL
+#define GET_IntelSubgroupAvcBuiltins_IMPL
+
+struct IntelSubgroupAvcWrapperBuiltin {
+ StringRef Name;
+ uint32_t Opcode;
+};
+
+#define GET_IntelSubgroupAvcWrapperBuiltins_DECL
+#define GET_IntelSubgroupAvcWrapperBuiltins_IMPL
+
struct AtomicFloatingBuiltin {
StringRef Name;
uint32_t Opcode;
@@ -697,7 +716,8 @@ static bool buildAtomicStoreInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
if (Call->isSpirvOp())
- return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call, Register(0));
+ return buildOpFromWrapper(MIRBuilder, SPIRV::OpAtomicStore, Call,
+ Register(0));
Register ScopeRegister =
buildConstantIntReg32(SPIRV::Scope::Device, MIRBuilder, GR);
@@ -2205,6 +2225,293 @@ static bool generateCoopMatrInst(const SPIRV::IncomingCall *Call,
IsSet ? TypeReg : Register(0), ImmArgs);
}
+static unsigned selectAvcMceResultConvertInst(SPIRV::AvcOpKind OpKind) {
+
+ if (OpKind == SPIRV::AvcOpKind::IME) {
+ return SPIRV::OpSubgroupAvcImeConvertToMceResultINTEL;
+ }
+ if (OpKind == SPIRV::AvcOpKind::REF) {
+ return SPIRV::OpSubgroupAvcRefConvertToMceResultINTEL;
+ }
+ return SPIRV::OpSubgroupAvcSicConvertToMceResultINTEL;
+}
+
+static std::pair<unsigned, unsigned>
+getMceConversionInstructions(SPIRV::AvcOpKind OpKind) {
+ using namespace SPIRV;
+
+ switch (OpKind) {
+ case AvcOpKind::IME:
+ return {SPIRV::OpSubgroupAvcImeConvertToMcePayloadINTEL,
+ SPIRV::OpSubgroupAvcMceConvertToImePayloadINTEL};
+ case AvcOpKind::REF:
+ return {SPIRV::OpSubgroupAvcRefConvertToMcePayloadINTEL,
+ SPIRV::OpSubgroupAvcMceConvertToRefPayloadINTEL};
+ default:
+ return {SPIRV::OpSubgroupAvcSicConvertToMcePayloadINTEL,
+ SPIRV::OpSubgroupAvcMceConvertToSicPayloadINTEL};
+ }
+}
+
+static bool generateAvcImeGetStreamout(const SPIRV::IncomingCall *Call,
+ StringRef &DemangledName,
+ unsigned FirstArgTy,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ MachineInstrBuilder MIB;
+ if (DemangledName.contains_insensitive("major_shape_motion_vectors")) {
+ MIB = MIRBuilder.buildInstr(
+ FirstArgTy == SPIRV::OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+ ? SPIRV::
+ OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL
+ : SPIRV::
+ OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL);
+ } else if (DemangledName.contains_insensitive("major_shape_distortion")) {
+ MIB = MIRBuilder.buildInstr(
+ FirstArgTy == SPIRV::OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+ ? SPIRV::
+ OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL
+ : SPIRV::
+ OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL);
+ } else if (DemangledName.contains_insensitive("major_shape_reference_ids")) {
+ MIB = MIRBuilder.buildInstr(
+ FirstArgTy == SPIRV::OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+ ? SPIRV::
+ OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL
+ : SPIRV::
+ OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL);
+ }
+ MIB.addDef(Call->ReturnRegister).addUse(GR->getSPIRVTypeID(Call->ReturnType));
+ for (auto Reg : Call->Arguments)
+ MIB.addUse(Reg);
+
+ return MIB;
+}
+
+// generate instruction for the evaluate type operation for the extension
+// SPV_INTEL_device_side_avc_motion_estimation
+static bool generateAvcEvaluateInstr(MachineIRBuilder &MIRBuilder,
+ unsigned Opcode,
+ const SPIRV::IncomingCall *Call,
+ SPIRVGlobalRegistry *GR) {
+ // evaluate opertations are handled separately
+ auto *MRI = MIRBuilder.getMRI();
+ SPIRVType *Type = GR->getOrCreateOpTypeVmeImageINTEL(
+ MIRBuilder); // there may be a need to reset the insertion point
+ Register SamplerReg;
+ SmallVector<Register, 7> ArgumentsVec;
+ Register Temp = MRI->createIncompleteVirtualRegister();
+
+ for (auto Arg : Call->Arguments) {
+ if (GR->getSPIRVTypeForVReg(Arg)->getOpcode() == SPIRV::OpTypeImage) {
+ Register VmeReg = createVirtualRegister(Type, GR, MRI, MRI->getMF());
+ GR->assignSPIRVTypeToVReg(Type, VmeReg, MRI->getMF());
+ // create OpVmeImageIntel with a temporary reg for the sampler which will
+ // then be replaced by the actual sampler
+ MIRBuilder.buildInstr(SPIRV::OpVmeImageINTEL)
+ .addDef(VmeReg)
+ .addUse(GR->getSPIRVTypeID(Type))
+ .addUse(Arg)
+ .addUse(Temp);
+ // MIB.addUse(VmeReg);
+ ArgumentsVec.push_back(VmeReg);
+ } else if (GR->getSPIRVTypeForVReg(Arg)->getOpcode() ==
+ SPIRV::OpTypeSampler) {
+ // sampler will not be added as the argument to the operation
+ SamplerReg = Arg;
+
+ } else {
+ ArgumentsVec.push_back(Arg);
+ // MIB.addUse(Arg);
+ }
+ }
+ MRI->replaceRegWith(Temp, SamplerReg);
+
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType));
+
+ for (Register Arg : ArgumentsVec) {
+ MIB.addUse(Arg);
+ }
+
+ return MIB;
+}
+
+static bool generateAvcSicConfigureIpeInstr(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+
+ unsigned NumArgs = Call->Arguments.size();
+ auto MIB = MIRBuilder.buildInstr(
+ NumArgs == 8 ? SPIRV::OpSubgroupAvcSicConfigureIpeLumaINTEL
+ : SPIRV::OpSubgroupAvcSicConfigureIpeLumaChromaINTEL);
+ MIB.addDef(Call->ReturnRegister).addUse(GR->getSPIRVTypeID(Call->ReturnType));
+ for (auto Reg : Call->Arguments)
+ MIB.addUse(Reg);
+ return MIB;
+}
+
+static inline SPIRV::AvcOpKind getAvcOpKind(const StringRef &DemangledName) {
+ if (DemangledName.contains_insensitive("_ime_"))
+ return SPIRV::AvcOpKind::IME;
+ if (DemangledName.contains_insensitive("_ref_"))
+ return SPIRV::AvcOpKind::REF;
+ if (DemangledName.contains_insensitive("_sic_"))
+ return SPIRV::AvcOpKind::SIC;
+ return SPIRV::AvcOpKind::UNKNOWN;
+}
+
+static SPIRVType *getSubgroupAVCIntelTyKind(SPIRVType *SpvTy,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ unsigned Opc = SpvTy->getOpcode();
+ if (Opc == SPIRV::OpTypeAvcImePayloadINTEL ||
+ Opc == SPIRV::OpTypeAvcRefPayloadINTEL ||
+ Opc == SPIRV::OpTypeAvcSicPayloadINTEL)
+ return GR->getOrCreateOpTypeAvcMcePayloadINTEL(MIRBuilder);
+ return GR->getOrCreateOpTypeAvcMceResultINTEL(MIRBuilder);
+}
+
+// generates instruction for builtin where the last argument is payload
+static bool generateAvcPayloadWrapperInst(const SPIRV::IncomingCall *Call,
+ SPIRVGlobalRegistry *GR,
+ MachineIRBuilder &MIRBuilder,
+ SPIRV::AvcOpKind OpKind,
+ unsigned AvcOpcode) {
+ MachineInstrBuilder MIB;
+ auto *MRI = MIRBuilder.getMRI();
+ const SPIRVType *MceTyKind =
+ GR->getOrCreateOpTypeAvcMcePayloadINTEL(MIRBuilder);
+ Register AvcPayload = createVirtualRegister(MceTyKind, GR, MRI, MRI->getMF());
+ Register LastArg = Call->Arguments[Call->Arguments.size() - 1];
+
+ auto [ToMceConvertInst, FromMceConvertInst] =
+ getMceConversionInstructions(OpKind);
+
+ MIRBuilder.buildInstr(ToMceConvertInst)
+ .addDef(AvcPayload)
+ .addUse(GR->getSPIRVTypeID(MceTyKind))
+ .addUse(LastArg);
+
+ auto TempReg = createVirtualRegister(MceTyKind, GR, MRI, MRI->getMF());
+
+ MIB = MIRBuilder.buildInstr(AvcOpcode).addDef(TempReg).addUse(
+ GR->getSPIRVTypeID(MceTyKind));
+
+ for (unsigned Idx = 0; Idx < Call->Arguments.size() - 1; Idx++)
+ MIB.addUse(Call->Arguments[Idx]);
+
+ MIB.addUse(AvcPayload);
+
+ MIRBuilder.buildInstr(FromMceConvertInst)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType))
+ .addUse(TempReg);
+
+ return MIB;
+}
+
+// generates instruction for Avc Wrapper instructions where last argument is
+// not payload
+static bool generateAvcResultWrapperInst(const SPIRV::IncomingCall *Call,
+ SPIRV::AvcOpKind OpKind,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR,
+ unsigned MceOpcode) {
+ MachineInstrBuilder MIB;
+ Register LastArg = Call->Arguments[Call->Arguments.size() - 1];
+ SPIRVType *MceTyKind = GR->getOrCreateOpTypeAvcMceResultINTEL(MIRBuilder);
+ auto *MRI = MIRBuilder.getMRI();
+
+ unsigned ToMceConvertInst;
+ ToMceConvertInst = selectAvcMceResultConvertInst(OpKind);
+
+ auto AvcConvertReg = createVirtualRegister(MceTyKind, GR, MRI, MRI->getMF());
+ MIRBuilder.buildInstr(ToMceConvertInst)
+ .addDef(AvcConvertReg)
+ .addUse(GR->getSPIRVTypeID(MceTyKind))
+ .addUse(LastArg);
+ MIB = MIRBuilder.buildInstr(MceOpcode)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType));
+ for (unsigned Idx = 0; Idx < Call->Arguments.size() - 1; Idx++)
+ MIB.addUse(Call->Arguments[Idx]);
+
+ MIB.addUse(AvcConvertReg);
+ ;
+ return MIB;
+}
+
+static bool generateIntelSubgroupAvcWrapper(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+
+ const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+ StringRef DemangledName = Builtin->Name;
+ const SPIRV::IntelSubgroupAvcWrapperBuiltin AvcSubgroupWrapper =
+ *SPIRV::lookupIntelSubgroupAvcWrapperBuiltin(Builtin->Name);
+ unsigned Opcode = AvcSubgroupWrapper.Opcode;
+
+ const SPIRV::AvcOpKind OpKind = getAvcOpKind(DemangledName);
+ Register LastArg = Call->Arguments[Call->Arguments.size() - 1];
+ const SPIRVType *MceTyKind = getSubgroupAVCIntelTyKind(
+ GR->getSPIRVTypeForVReg(LastArg), MIRBuilder, GR);
+
+ if (MceTyKind->getOpcode() == SPIRV::OpTypeAvcMcePayloadINTEL) {
+ return generateAvcPayloadWrapperInst(Call, GR, MIRBuilder, OpKind, Opcode);
+ }
+ return generateAvcResultWrapperInst(Call, OpKind, MIRBuilder, GR, Opcode);
+}
+
+static bool generateIntelSubgroupAvc(const SPIRV::IncomingCall *Call,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+
+ const SPIRV::DemangledBuiltin *Builtin = Call->Builtin;
+ StringRef DemangledName = Builtin->Name;
+ const SPIRV::IntelSubgroupAvcBuiltin AvcSubgroup =
+ *SPIRV::lookupIntelSubgroupAvcBuiltin(Builtin->Name);
+ unsigned Opcode = AvcSubgroup.Opcode;
+
+ // sic configure ipe instruction has same demangled name for multiple
+ // instructions
+ if (DemangledName.contains_insensitive("sic_configure_ipe")) {
+ return generateAvcSicConfigureIpeInstr(Call, MIRBuilder, GR);
+ }
+
+ // instructions with ime_get_streamout have the same demangled name for
+ // multiple instructions, which are differentiated based on the arguments
+ if (DemangledName.contains_insensitive("ime_get_streamout")) {
+
+ unsigned FirstArgTy =
+ GR->getSPIRVTypeForVReg(Call->Arguments[0])->getOpcode();
+ return generateAvcImeGetStreamout(Call, DemangledName, FirstArgTy,
+ MIRBuilder, GR);
+ }
+
+ if (AvcSubgroup.IsEvaluate) {
+ if (DemangledName.contains_insensitive("multi_reference")) {
+ if (AvcSubgroup.IsSic && Call->Arguments.size() == 5)
+ Opcode =
+ SPIRV::OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL;
+ else if (AvcSubgroup.IsRef && Call->Arguments.size() == 5)
+ Opcode =
+ SPIRV::OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL;
+ }
+ return generateAvcEvaluateInstr(MIRBuilder, Opcode, Call, GR);
+ }
+
+ auto MIB = MIRBuilder.buildInstr(Opcode)
+ .addDef(Call->ReturnRegister)
+ .addUse(GR->getSPIRVTypeID(Call->ReturnType));
+
+ for (auto Reg : Call->Arguments)
+ MIB.addUse(Reg);
+
+ return MIB;
+}
+
static bool generateSpecConstantInst(const SPIRV::IncomingCall *Call,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -2877,6 +3184,10 @@ std::optional<bool> lowerBuiltin(const StringRef DemangledCall,
return generateBindlessImageINTELInst(Call.get(), MIRBuilder, GR);
case SPIRV::TernaryBitwiseINTEL:
return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR);
+ case SPIRV::IntelSubgroupsAvc:
+ return generateIntelSubgroupAvc(Call.get(), MIRBuilder, GR);
+ case SPIRV::IntelSubgroupsAvcWrapper:
+ return generateIntelSubgroupAvcWrapper(Call.get(), MIRBuilder, GR);
}
return false;
}
@@ -3002,6 +3313,86 @@ static SPIRVType *getSamplerType(MachineIRBuilder &MIRBuilder,
return GR->getOrCreateOpTypeSampler(MIRBuilder);
}
+static SPIRVType *getAvcMcePayload(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ // Create or get an existing type from GlobalRegistry.
+
+ return GR->getOrCreateOpTypeAvcMcePayloadINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcImePayloadINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcImePayloadINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcRefPayloadINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcRefPayloadINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcSicPayloadINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcSicPayloadINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcMceResultINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcMceResultINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcImeResultINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcImeResultINTEL(MIRBuilder);
+}
+
+static SPIRVType *
+getAvcImeResultSingleReferenceStreamoutINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcImeResultSingleReferenceStreamoutINTEL(
+ MIRBuilder);
+}
+
+static SPIRVType *
+getAvcImeResultDualReferenceStreamoutINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcImeResultDualReferenceStreamoutINTEL(
+ MIRBuilder);
+}
+
+static SPIRVType *
+getAvcImeSingleReferenceStreaminINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcImeSingleReferenceStreaminINTEL(MIRBuilder);
+}
+
+static SPIRVType *
+getAvcImeDualReferenceStreaminINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcImeDualReferenceStreaminINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcRefResultINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcRefResultINTEL(MIRBuilder);
+}
+
+static SPIRVType *getAvcSicResultINTEL(const TargetExtType *ExtensionType,
+ MachineIRBuilder &MIRBuilder,
+ SPIRVGlobalRegistry *GR) {
+ return GR->getOrCreateOpTypeAvcSicResultINTEL(MIRBuilder);
+}
+
static SPIRVType *getPipeType(const TargetExtType *ExtensionType,
MachineIRBuilder &MIRBuilder,
SPIRVGlobalRegistry *GR) {
@@ -3246,6 +3637,46 @@ SPIRVType *lowerBuiltinType(const Type *OpaqueType,
case SPIRV::OpTypeCooperativeMatrixKHR:
TargetType = getCoopMatrType(BuiltinType, MIRBuilder, GR);
break;
+ case SPIRV::OpTypeAvcMcePayloadINTEL:
+ TargetType = getAvcMcePayload(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcImePayloadINTEL:
+ TargetType = getAvcImePayloadINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcRefPayloadINTEL:
+ TargetType = getAvcRefPayloadINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcSicPayloadINTEL:
+ TargetType = getAvcSicPayloadINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcMceResultINTEL:
+ TargetType = getAvcMceResultINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcImeResultINTEL:
+ TargetType = getAvcImeResultINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcImeResultSingleReferenceStreamoutINTEL:
+ TargetType = getAvcImeResultSingleReferenceStreamoutINTEL(BuiltinType,
+ MIRBuilder, GR);
+ break;
+ case OpTypeAvcImeResultDualReferenceStreamoutINTEL:
+ TargetType = getAvcImeResultDualReferenceStreamoutINTEL(BuiltinType,
+ MIRBuilder, GR);
+ break;
+ case OpTypeAvcImeSingleReferenceStreaminINTEL:
+ TargetType =
+ getAvcImeSingleReferenceStreaminINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcImeDualReferenceStreaminINTEL:
+ TargetType =
+ getAvcImeDualReferenceStreaminINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcRefResultINTEL:
+ TargetType = getAvcRefResultINTEL(BuiltinType, MIRBuilder, GR);
+ break;
+ case OpTypeAvcSicResultINTEL:
+ TargetType = getAvcSicResultINTEL(BuiltinType, MIRBuilder, GR);
+ break;
default:
TargetType =
getNonParameterizedType(BuiltinType, TypeRecord, MIRBuilder, GR);
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h
index 1a8641a8328dd..e2980a997a077 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.h
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.h
@@ -47,6 +47,10 @@ std::tuple<int, unsigned, unsigned>
mapBuiltinToOpcode(const StringRef DemangledCall,
SPIRV::InstructionSet::InstructionSet Set);
+// This enum represents different types of operations in the extension
+// SPV_INTEL_device_side_avc_motion_estimation
+enum AvcOpKind { IME, REF, SIC, UNKNOWN };
+
/// Parses the provided \p ArgIdx argument base type in the \p DemangledCall
/// skeleton. A base type is either a basic type (e.g. i32 for int), pointer
/// element type (e.g. i8 for char*), or builtin type (TargetExtType).
diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
index b504e7b04d336..d4dca406d4ff6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
+++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td
@@ -68,6 +68,8 @@ def ICarryBorrow : BuiltinGroup;
def ExtendedBitOps : BuiltinGroup;
def BindlessINTEL : BuiltinGroup;
def TernaryBitwiseINTEL : BuiltinGroup;
+def IntelSubgroupsAvc: BuiltinGroup;
+def IntelSubgroupsAvcWrapper: BuiltinGroup;
//===----------------------------------------------------------------------===//
// Class defining a demangled builtin record. The information in the record
@@ -1624,6 +1626,20 @@ def : BuiltinType<"spirv.SampledImage", OpTypeSampledImage>;
def : BuiltinType<"spirv.Pipe", OpTypePipe>;
def : BuiltinType<"spirv.CooperativeMatrixKHR", OpTypeCooperativeMatrixKHR>;
+//Types from extension SPV_INTEL_device_side_avc_motion_estimation
+def : BuiltinType<"spirv.AvcMcePayloadINTEL", OpTypeAvcMcePayloadINTEL>;
+def : BuiltinType<"spirv.AvcImePayloadINTEL", OpTypeAvcImePayloadINTEL>;
+def : BuiltinType<"spirv.AvcRefPayloadINTEL", OpTypeAvcRefPayloadINTEL>;
+def : BuiltinType<"spirv.AvcSicPayloadINTEL", OpTypeAvcSicPayloadINTEL>;
+def : BuiltinType<"spirv.AvcMceResultINTEL", OpTypeAvcMceResultINTEL>;
+def : BuiltinType<"spirv.AvcImeResultINTEL", OpTypeAvcImeResultINTEL>;
+def : BuiltinType<"spirv.AvcImeResultSingleReferenceStreamoutINTEL", OpTypeAvcImeResultSingleReferenceStreamoutINTEL>;
+def : BuiltinType<"spirv.AvcImeResultDualReferenceStreamoutINTEL", OpTypeAvcImeResultDualReferenceStreamoutINTEL>;
+def : BuiltinType<"spirv.AvcImeSingleReferenceStreaminINTEL", OpTypeAvcImeSingleReferenceStreaminINTEL>;
+def : BuiltinType<"spirv.AvcImeDualReferenceStreaminINTEL", OpTypeAvcImeDualReferenceStreaminINTEL>;
+def : BuiltinType<"spirv.AvcRefResultINTEL", OpTypeAvcRefResultINTEL>;
+def : BuiltinType<"spirv.AvcSicResultINTEL", OpTypeAvcSicResultINTEL>;
+
//===----------------------------------------------------------------------===//
// Class matching an OpenCL builtin type name to an equivalent SPIR-V
// builtin type literal.
@@ -1795,3 +1811,262 @@ defm : DemangledIntegerDotProductBuiltin<"_acc_sat_4x8packed_uu_uint", 3, 4, OpU
defm : DemangledIntegerDotProductBuiltin<"_acc_sat_4x8packed_ss_int", 3, 4, OpSDotAccSat>;
defm : DemangledIntegerDotProductBuiltin<"_acc_sat_4x8packed_us_int", 3, 4, OpSUDotAccSat>;
defm : DemangledIntegerDotProductBuiltin<"_acc_sat_4x8packed_su_int", 3, 4, OpSUDotAccSat>;
+
+// cl_intel_device_side_avc_motion_estimation
+class IntelSubgroupAvcBuiltin<string name, Op operation> {
+ string Name = name;
+ Op Opcode = operation;
+
+ bit IsRef = !or(!eq(operation, OpSubgroupAvcFmeInitializeINTEL),
+ !eq(operation, OpSubgroupAvcBmeInitializeINTEL),
+ !eq(operation, OpSubgroupAvcRefConvertToMcePayloadINTEL),
+ !eq(operation, OpSubgroupAvcRefSetBidirectionalMixDisableINTEL),
+ !eq(operation, OpSubgroupAvcRefSetBilinearFilterEnableINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithDualReferenceINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL),
+ !eq(operation, OpSubgroupAvcRefConvertToMceResultINTEL));
+
+ bit IsSic = !or(!eq(operation, OpSubgroupAvcSicInitializeINTEL),
+ !eq(operation, OpSubgroupAvcSicConfigureSkcINTEL),
+ !eq(operation, OpSubgroupAvcSicConfigureIpeLumaINTEL),
+ !eq(operation, OpSubgroupAvcSicConfigureIpeLumaChromaINTEL),
+ !eq(operation, OpSubgroupAvcSicGetMotionVectorMaskINTEL),
+ !eq(operation, OpSubgroupAvcSicConvertToMcePayloadINTEL),
+ !eq(operation, OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL),
+ !eq(operation, OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL),
+ !eq(operation, OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL),
+ !eq(operation, OpSubgroupAvcSicSetBilinearFilterEnableINTEL),
+ !eq(operation, OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL),
+ !eq(operation, OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateIpeINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithDualReferenceINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL),
+ !eq(operation, OpSubgroupAvcSicConvertToMceResultINTEL),
+ !eq(operation, OpSubgroupAvcSicGetIpeLumaShapeINTEL),
+ !eq(operation, OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL),
+ !eq(operation, OpSubgroupAvcSicGetBestIpeChromaDistortionINTEL),
+ !eq(operation, OpSubgroupAvcSicGetPackedIpeLumaModesINTEL),
+ !eq(operation, OpSubgroupAvcSicGetIpeChromaModeINTEL),
+ !eq(operation, OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL),
+ !eq(operation, OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL),
+ !eq(operation, OpSubgroupAvcSicGetInterRawSadsINTEL));
+
+ bit IsEvaluate = !or(!eq(operation, OpSubgroupAvcImeEvaluateWithSingleReferenceINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithDualReferenceINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithSingleReferenceStreamoutINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithDualReferenceStreamoutINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminoutINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithDualReferenceStreaminoutINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithDualReferenceINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL),
+ !eq(operation, OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateIpeINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithDualReferenceINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL),
+ !eq(operation, OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminINTEL),
+ !eq(operation, OpSubgroupAvcImeEvaluateWithDualReferenceStreaminINTEL));
+}
+
+// Table gathering all the Intel sub group builtins.
+def IntelSubgroupAvcBuiltins : GenericTable {
+ let FilterClass = "IntelSubgroupAvcBuiltin";
+ let Fields = ["Name", "Opcode", "IsRef", "IsSic", "IsEvaluate"];
+}
+
+// Function to lookup group builtins by their name and set.
+def lookupIntelSubgroupAvcBuiltin : SearchIndex {
+ let Table = IntelSubgroupAvcBuiltins;
+ let Key = ["Name"];
+}
+
+
+// Multiclass used to define incoming builtin records for the SPV_INTEL_device_side_avc_motion_estimation extension
+// and corresponding work/sub group builtin records.
+multiclass DemangledIntelSubgroupsAvcBuiltin<string name, bits<8> minNumArgs, bits<8> maxNumArgs, Op operation> {
+ def : DemangledBuiltin<!strconcat("intel_sub_group_avc_", name), OpenCL_std, IntelSubgroupsAvc, minNumArgs, maxNumArgs>;
+ def : IntelSubgroupAvcBuiltin<!strconcat("intel_sub_group_avc_", name), operation>;
+}
+
+// cl_intel_subgroup_avc_mce
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_inter_base_multi_reference_penalty", 2, 5, OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_inter_base_multi_reference_penalty", 2, 5, OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_inter_shape_penalty", 2, 5, OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_inter_shape_penalty", 2, 5, OpSubgroupAvcMceSetInterShapePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_inter_direction_penalty", 2, 5, OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_inter_direction_penalty", 2, 5, OpSubgroupAvcMceSetInterDirectionPenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_intra_luma_shape_penalty", 2, 5, OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_inter_motion_vector_cost_table", 2, 5, OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_high_penalty_cost_table", 0, 3, OpSubgroupAvcMceGetDefaultHighPenaltyCostTableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_medium_penalty_cost_table", 0, 3, OpSubgroupAvcMceGetDefaultMediumPenaltyCostTableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_low_penalty_cost_table", 0, 3, OpSubgroupAvcMceGetDefaultLowPenaltyCostTableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_motion_vector_cost_function", 4, 7, OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_intra_luma_mode_penalty", 2, 5, OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_non_dc_luma_intra_penalty", 0, 3, OpSubgroupAvcMceGetDefaultNonDcLumaIntraPenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_default_intra_chroma_mode_base_penalty", 0, 3, OpSubgroupAvcMceGetDefaultIntraChromaModeBasePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_ac_only_haar", 1, 4, OpSubgroupAvcMceSetAcOnlyHaarINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_source_interlaced_field_polarity", 2, 5, OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_single_reference_interlaced_field_polarity", 2, 5, OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_set_dual_reference_interlaced_field_polarities", 3, 6, OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_convert_to_ime_payload", 1, 4, OpSubgroupAvcMceConvertToImePayloadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_convert_to_ime_result", 1, 4, OpSubgroupAvcMceConvertToImeResultINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_convert_to_ref_payload", 1, 4, OpSubgroupAvcMceConvertToRefPayloadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_convert_to_ref_result", 1, 4, OpSubgroupAvcMceConvertToRefResultINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_convert_to_sic_payload", 1, 4, OpSubgroupAvcMceConvertToSicPayloadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_convert_to_sic_result", 1, 4, OpSubgroupAvcMceConvertToSicResultINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_motion_vectors", 1, 4, OpSubgroupAvcMceGetMotionVectorsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_distortions", 1, 4, OpSubgroupAvcMceGetInterDistortionsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_best_inter_distortions", 1, 4, OpSubgroupAvcMceGetBestInterDistortionsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_major_shape", 1, 4, OpSubgroupAvcMceGetInterMajorShapeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_minor_shape", 1, 4, OpSubgroupAvcMceGetInterMinorShapeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_directions", 1, 4, OpSubgroupAvcMceGetInterDirectionsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_motion_vector_count", 1, 4, OpSubgroupAvcMceGetInterMotionVectorCountINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_reference_ids", 1, 4, OpSubgroupAvcMceGetInterReferenceIdsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"mce_get_inter_reference_interlaced_field_polarities", 3, 6, OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL>;
+
+//cl_intel_sub_group_avc_ime
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_initialize", 3, 6, OpSubgroupAvcImeInitializeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_set_single_reference", 3, 6, OpSubgroupAvcImeSetSingleReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_set_dual_reference", 4, 7, OpSubgroupAvcImeSetDualReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_ref_window_size", 2, 5, OpSubgroupAvcImeRefWindowSizeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_adjust_ref_offset", 4, 7, OpSubgroupAvcImeAdjustRefOffsetINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_convert_to_mce_payload", 1, 4, OpSubgroupAvcImeConvertToMcePayloadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_set_max_motion_vector_count", 2, 5, OpSubgroupAvcImeSetMaxMotionVectorCountINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_set_unidirectional_mix_disable", 1, 4, OpSubgroupAvcImeSetUnidirectionalMixDisableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_set_early_search_termination_threshold", 2, 5, OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_set_weighted_sad", 2, 5, OpSubgroupAvcImeSetWeightedSadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_single_reference", 3, 6, OpSubgroupAvcImeEvaluateWithSingleReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_dual_reference", 4, 7, OpSubgroupAvcImeEvaluateWithDualReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_single_reference_streamin", 3, 6, OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_dual_reference_streamin", 4, 7, OpSubgroupAvcImeEvaluateWithDualReferenceStreaminINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_single_reference_streamout", 3, 6, OpSubgroupAvcImeEvaluateWithSingleReferenceStreamoutINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_dual_reference_streamout", 4, 7, OpSubgroupAvcImeEvaluateWithDualReferenceStreamoutINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_single_reference_streaminout", 5, 8, OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminoutINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_evaluate_with_dual_reference_streaminout", 4, 7, OpSubgroupAvcImeEvaluateWithDualReferenceStreaminoutINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_convert_to_mce_result", 5, 8, OpSubgroupAvcImeConvertToMceResultINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_single_reference_streamin", 1, 4, OpSubgroupAvcImeGetSingleReferenceStreaminINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_dual_reference_streamin", 1, 4, OpSubgroupAvcImeGetDualReferenceStreaminINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_strip_single_reference_streamout", 1, 4, OpSubgroupAvcImeStripSingleReferenceStreamoutINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_strip_dual_reference_streamout", 1, 4, OpSubgroupAvcImeStripDualReferenceStreamoutINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_streamout_major_shape_motion_vectors", 2, 5, OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_streamout_major_shape_distortions", 3, 6, OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_streamout_major_shape_reference_ids", 2, 5, OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_streamout_major_shape_motion_vectors", 3, 6, OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_streamout_major_shape_distortions", 2, 5, OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_streamout_major_shape_reference_ids", 3, 6, OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_border_reached", 2, 5, OpSubgroupAvcImeGetBorderReachedINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_truncated_search_indication", 1, 4, OpSubgroupAvcImeGetTruncatedSearchIndicationINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_unidirectional_early_search_termination", 1, 4, OpSubgroupAvcImeGetUnidirectionalEarlySearchTerminationINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_weighting_pattern_minimum_motion_vector", 1, 4, OpSubgroupAvcImeGetWeightingPatternMinimumMotionVectorINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ime_get_weighting_pattern_minimum_distortion", 1, 4, OpSubgroupAvcImeGetWeightingPatternMinimumDistortionINTEL>;
+
+//cl_intel_sub_group_avc_ref
+defm : DemangledIntelSubgroupsAvcBuiltin<"fme_initialize", 7, 10, OpSubgroupAvcFmeInitializeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"bme_initialize", 8, 11, OpSubgroupAvcBmeInitializeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_convert_to_mce_payload", 1, 4, OpSubgroupAvcRefConvertToMcePayloadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_set_bidirectional_mix_disable", 1, 4, OpSubgroupAvcRefSetBidirectionalMixDisableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_set_bilinear_filter_enable", 1, 4, OpSubgroupAvcRefSetBilinearFilterEnableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_evaluate_with_single_reference", 3, 6, OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_evaluate_with_dual_reference", 4, 7, OpSubgroupAvcRefEvaluateWithDualReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_evaluate_with_multi_reference", 3, 6, OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_evaluate_with_multi_reference_interlaced", 4, 7, OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"ref_convert_to_mce_result", 1, 4, OpSubgroupAvcRefConvertToMceResultINTEL>;
+
+//cl_intel_subgroup_avc_sic
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_initialize", 1, 4, OpSubgroupAvcSicInitializeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_configure_skc", 6, 9, OpSubgroupAvcSicConfigureSkcINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_configure_ipe", 8, 11, OpSubgroupAvcSicConfigureIpeLumaINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_configure_ipe", 11, 14, OpSubgroupAvcSicConfigureIpeLumaChromaINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_motion_vector_mask", 2, 5, OpSubgroupAvcSicGetMotionVectorMaskINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_convert_to_mce_payload", 1, 4, OpSubgroupAvcSicConvertToMcePayloadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_set_intra_luma_shape_penalty", 1, 4, OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_set_intra_luma_mode_cost_function", 2, 5, OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_set_intra_chroma_mode_cost_function", 2, 5, OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_set_bilinear_filter_enable", 4, 7, OpSubgroupAvcSicSetBilinearFilterEnableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_set_skc_forward_transform_enable", 1, 4, OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_set_block_based_raw_skip_sad", 2, 5, OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_evaluate_ipe", 2, 5, OpSubgroupAvcSicEvaluateIpeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_evaluate_with_single_reference", 2, 5, OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_evaluate_with_dual_reference", 4, 7, OpSubgroupAvcSicEvaluateWithDualReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_evaluate_with_multi_reference", 3, 6, OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_evaluate_with_multi_reference_interlaced", 4, 7, OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_convert_to_mce_result", 1, 4, OpSubgroupAvcSicConvertToMceResultINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_ipe_luma_shape", 1, 4, OpSubgroupAvcSicGetIpeLumaShapeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_best_ipe_luma_distortion", 1, 4, OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_best_ipe_chroma_distortion", 1, 4, OpSubgroupAvcSicGetBestIpeChromaDistortionINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_packed_ipe_luma_modes", 1, 4, OpSubgroupAvcSicGetPackedIpeLumaModesINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_ipe_chroma_mode", 1, 4, OpSubgroupAvcSicGetIpeChromaModeINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_packed_skc_luma_count_threshold", 1, 4, OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_packed_skc_luma_sum_threshold", 1, 4, OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL>;
+defm : DemangledIntelSubgroupsAvcBuiltin<"sic_get_inter_raw_sads", 1, 4, OpSubgroupAvcSicGetInterRawSadsINTEL>;
+
+
+class IntelSubgroupAvcWrapperBuiltin<string name, Op operation> {
+ string Name = name;
+ Op Opcode = operation;
+}
+
+
+def IntelSubgroupAvcWrapperBuiltins : GenericTable {
+ let FilterClass = "IntelSubgroupAvcWrapperBuiltin";
+ let Fields = ["Name", "Opcode"];
+}
+
+// Function to lookup group builtins by their name and set.
+def lookupIntelSubgroupAvcWrapperBuiltin : SearchIndex {
+ let Table = IntelSubgroupAvcWrapperBuiltins;
+ let Key = ["Name"];
+}
+
+
+// Multiclass used to define incoming builtin records for wrapper functions the SPV_INTEL_device_side_avc_motion_estimation extension
+// and corresponding work/sub group builtin records.
+multiclass DemangledIntelSubgroupsAvcWrapperBuiltin<string name, string Kind, bits<8> minNumArgs, bits<8> maxNumArgs, Op operation> {
+ def : DemangledBuiltin<!strconcat("intel_sub_group_avc_", Kind, name), OpenCL_std, IntelSubgroupsAvcWrapper, minNumArgs, maxNumArgs>;
+ def : IntelSubgroupAvcWrapperBuiltin<!strconcat("intel_sub_group_avc_", Kind, name), operation>;
+}
+
+
+//wrapper function avc
+foreach Kind = ["sic", "ref", "ime"] in {
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_inter_base_multi_reference_penalty", Kind, 2, 5, OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_inter_base_multi_reference_penalty", Kind, 2, 5, OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_inter_shape_penalty", Kind, 2, 5, OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_inter_shape_penalty", Kind, 2, 5, OpSubgroupAvcMceSetInterShapePenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_inter_direction_penalty", Kind, 2, 5, OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_inter_direction_penalty", Kind, 2, 5, OpSubgroupAvcMceSetInterDirectionPenaltyINTEL>;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_intra_luma_shape_penalty", Kind, 2, 5, OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_inter_motion_vector_cost_table", Kind, 2, 5, OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_high_penalty_cost_table", Kind, 0, 3, OpSubgroupAvcMceGetDefaultHighPenaltyCostTableINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_medium_penalty_cost_table", Kind, 0, 3, OpSubgroupAvcMceGetDefaultMediumPenaltyCostTableINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_low_penalty_cost_table", Kind, 0, 3, OpSubgroupAvcMceGetDefaultLowPenaltyCostTableINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_motion_vector_cost_function", Kind, 4, 7, OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_intra_luma_mode_penalty", Kind, 2, 5, OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_non_dc_luma_intra_penalty", Kind, 0, 3, OpSubgroupAvcMceGetDefaultNonDcLumaIntraPenaltyINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_default_intra_chroma_mode_base_penalty", Kind, 0, 3, OpSubgroupAvcMceGetDefaultIntraChromaModeBasePenaltyINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_ac_only_haar", Kind, 1, 4, OpSubgroupAvcMceSetAcOnlyHaarINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_source_interlaced_field_polarity", Kind, 2, 5, OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_single_reference_interlaced_field_polarity", Kind, 2, 5, OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_set_dual_reference_interlaced_field_polarities", Kind, 3, 6, OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_convert_to_ime_payload", Kind, 1, 4, OpSubgroupAvcMceConvertToImePayloadINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_convert_to_ime_result", Kind, 1, 4, OpSubgroupAvcMceConvertToImeResultINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_convert_to_ref_payload", Kind, 1, 4, OpSubgroupAvcMceConvertToRefPayloadINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_convert_to_ref_result", Kind, 1, 4, OpSubgroupAvcMceConvertToRefResultINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_convert_to_sic_payload", Kind, 1, 4, OpSubgroupAvcMceConvertToSicPayloadINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_convert_to_sic_result", Kind, 1, 4, OpSubgroupAvcMceConvertToSicResultINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_motion_vectors", Kind, 1, 4, OpSubgroupAvcMceGetMotionVectorsINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_distortions", Kind, 1, 4, OpSubgroupAvcMceGetInterDistortionsINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_best_inter_distortions", Kind, 1, 4, OpSubgroupAvcMceGetBestInterDistortionsINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_major_shape", Kind, 1, 4, OpSubgroupAvcMceGetInterMajorShapeINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_minor_shape", Kind, 1, 4, OpSubgroupAvcMceGetInterMinorShapeINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_directions", Kind, 1, 4, OpSubgroupAvcMceGetInterDirectionsINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_motion_vector_count", Kind, 1, 4, OpSubgroupAvcMceGetInterMotionVectorCountINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_reference_ids", Kind, 1, 4, OpSubgroupAvcMceGetInterReferenceIdsINTEL >;
+defm : DemangledIntelSubgroupsAvcWrapperBuiltin<"_get_inter_reference_interlaced_field_polarities", Kind, 3, 6, OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL >;
+}
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 53e88aa485568..024cf61605060 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -94,7 +94,10 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
{"SPV_INTEL_fp_max_error",
SPIRV::Extension::Extension::SPV_INTEL_fp_max_error},
{"SPV_INTEL_ternary_bitwise_function",
- SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function}};
+ SPIRV::Extension::Extension::SPV_INTEL_ternary_bitwise_function},
+ {"SPV_INTEL_device_side_avc_motion_estimation",
+ SPIRV::Extension::Extension::
+ SPV_INTEL_device_side_avc_motion_estimation}};
bool SPIRVExtensionsParser::parse(cl::Option &O, StringRef ArgName,
StringRef ArgValue,
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
index cc01a6d0bac23..1eb3f4b1b533a 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
@@ -1454,6 +1454,371 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeDeviceEvent(
return NewMI;
}
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeVmeImageINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcVmeImage);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeVmeImageINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcMcePayloadINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcMcePayload);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcMcePayloadINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcImePayloadINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcImePayload);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcImePayloadINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcRefPayloadINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcRefPayload);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcRefPayloadINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcSicPayloadINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcSicPayload);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcSicPayloadINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcMceResultINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcMceResult);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcMceResultINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcImeResultINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcImeResult);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcImeResultINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *
+SPIRVGlobalRegistry::getOrCreateOpTypeAvcImeResultSingleReferenceStreamoutINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(
+ SPIRV::SpecialTypeKind::STK_AvcImeResultSingleReferenceStreamout);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder
+ .buildInstr(SPIRV::OpTypeAvcImeResultSingleReferenceStreamoutINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *
+SPIRVGlobalRegistry::getOrCreateOpTypeAvcImeResultDualReferenceStreamoutINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(
+ SPIRV::SpecialTypeKind::STK_AvcImeResultDualReferenceStreamout);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder
+ .buildInstr(SPIRV::OpTypeAvcImeResultDualReferenceStreamoutINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *
+SPIRVGlobalRegistry::getOrCreateOpTypeAvcImeSingleReferenceStreaminINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(
+ SPIRV::SpecialTypeKind::STK_AvcImeSingleReferenceStreamin);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder
+ .buildInstr(SPIRV::OpTypeAvcImeSingleReferenceStreaminINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *
+SPIRVGlobalRegistry::getOrCreateOpTypeAvcImeDualReferenceStreaminINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(
+ SPIRV::SpecialTypeKind::STK_AvcImeDualReferenceStreamin);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder
+ .buildInstr(SPIRV::OpTypeAvcImeDualReferenceStreaminINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcRefResultINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcRefResult);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcRefResultINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
+SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeAvcSicResultINTEL(
+ MachineIRBuilder &MIRBuilder) {
+ auto Key = SPIRV::irhandle_avc(SPIRV::SpecialTypeKind::STK_AvcSicResult);
+
+ if (const MachineInstr *MI = findMI(Key, &MIRBuilder.getMF()))
+ return MI;
+
+ const SPIRVSubtarget &ST =
+ cast<SPIRVSubtarget>(MIRBuilder.getMF().getSubtarget());
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ MIRBuilder.buildInstr(SPIRV::OpExtension)
+ .addImm(SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::Groups);
+ MIRBuilder.buildInstr(SPIRV::OpCapability)
+ .addImm(SPIRV::Capability::SubgroupAvcMotionEstimationINTEL);
+ }
+ const MachineInstr *NewMI =
+ createOpType(MIRBuilder, [&](MachineIRBuilder &MIRBuilder) {
+ return MIRBuilder.buildInstr(SPIRV::OpTypeAvcSicResultINTEL)
+ .addDef(createTypeVReg(MIRBuilder));
+ });
+ add(Key, NewMI);
+ return NewMI;
+}
+
SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(
SPIRVType *ImageType, MachineIRBuilder &MIRBuilder) {
auto Key = SPIRV::irhandle_sampled_image(
diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
index b05896fb7174c..93550e370ea55 100644
--- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
+++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h
@@ -600,6 +600,23 @@ class SPIRVGlobalRegistry : public SPIRVIRMapping {
getOrCreateOpTypePipe(MachineIRBuilder &MIRBuilder,
SPIRV::AccessQualifier::AccessQualifier AccQual);
SPIRVType *getOrCreateOpTypeDeviceEvent(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeVmeImageINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcMcePayloadINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcImePayloadINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcRefPayloadINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcSicPayloadINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcMceResultINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcImeResultINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcImeResultSingleReferenceStreamoutINTEL(
+ MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcImeResultDualReferenceStreamoutINTEL(
+ MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcImeSingleReferenceStreaminINTEL(
+ MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcImeDualReferenceStreaminINTEL(
+ MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcRefResultINTEL(MachineIRBuilder &MIRBuilder);
+ SPIRVType *getOrCreateOpTypeAvcSicResultINTEL(MachineIRBuilder &MIRBuilder);
SPIRVType *getOrCreateOpTypeFunctionWithArgs(
const Type *Ty, SPIRVType *RetType,
const SmallVectorImpl<SPIRVType *> &ArgTypes,
diff --git a/llvm/lib/Target/SPIRV/SPIRVIRMapping.h b/llvm/lib/Target/SPIRV/SPIRVIRMapping.h
index 5e8e1c55d91c6..51ba2a7779b06 100644
--- a/llvm/lib/Target/SPIRV/SPIRVIRMapping.h
+++ b/llvm/lib/Target/SPIRV/SPIRVIRMapping.h
@@ -66,6 +66,19 @@ enum SpecialTypeKind {
STK_Value,
STK_MachineInstr,
STK_VkBuffer,
+ STK_AvcVmeImage,
+ STK_AvcMcePayload,
+ STK_AvcImePayload,
+ STK_AvcRefPayload,
+ STK_AvcSicPayload,
+ STK_AvcMceResult,
+ STK_AvcImeResult,
+ STK_AvcImeResultSingleReferenceStreamout,
+ STK_AvcImeResultDualReferenceStreamout,
+ STK_AvcImeSingleReferenceStreamin,
+ STK_AvcImeDualReferenceStreamin,
+ STK_AvcRefResult,
+ STK_AvcSicResult,
STK_Last = -1
};
@@ -150,6 +163,10 @@ inline IRHandle irhandle_vkbuffer(const Type *ElementType,
SpecialTypeKind::STK_VkBuffer);
}
+inline IRHandle irhandle_avc(SpecialTypeKind STK) {
+ return std::make_tuple(nullptr, 0U, STK);
+}
+
inline IRHandle handle(const Type *Ty) {
const Type *WrpTy = unifyPtrType(Ty);
return irhandle_ptr(WrpTy, Ty->getTypeID(), STK_Type);
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 53064ebb51271..e49a05a82dbb7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -209,7 +209,20 @@ def OpTypeCooperativeMatrixNV: Op<5358, (outs TYPE:$res),
def OpTypeCooperativeMatrixKHR: Op<4456, (outs TYPE:$res),
(ins TYPE:$compType, ID:$scope, ID:$rows, ID:$cols, ID:$use),
"$res = OpTypeCooperativeMatrixKHR $compType $scope $rows $cols $use">;
-
+//dsame
+def OpTypeVmeImageINTEL: Op<5700, (outs TYPE:$res), (ins), "$res = OpTypeVmeImageINTEL">;
+def OpTypeAvcMcePayloadINTEL: Op<5704, (outs TYPE:$res), (ins), "$res = OpTypeAvcMcePayloadINTEL">;
+def OpTypeAvcImePayloadINTEL: Op<5701, (outs TYPE:$res), (ins), "$res = OpTypeAvcImePayloadINTEL">;
+def OpTypeAvcRefPayloadINTEL: Op<5702, (outs TYPE:$res), (ins), "$res = OpTypeAvcRefPayloadINTEL">;
+def OpTypeAvcSicPayloadINTEL: Op<5704, (outs TYPE:$res), (ins), "$res = OpTypeAvcSicPayloadINTEL">;
+def OpTypeAvcMceResultINTEL: Op<5705, (outs TYPE:$res), (ins), "$res = OpTypeAvcMceResultINTEL">;
+def OpTypeAvcImeResultINTEL: Op<5706, (outs TYPE:$res), (ins), "$res = OpTypeAvcImeResultINTEL">;
+def OpTypeAvcImeResultSingleReferenceStreamoutINTEL: Op<5707, (outs TYPE:$res), (ins), "$res = OpTypeAvcImeResultSingleReferenceStreamoutINTEL">;
+def OpTypeAvcImeResultDualReferenceStreamoutINTEL: Op<5708, (outs TYPE:$res), (ins), "$res = OpTypeAvcImeResultDualReferenceStreamoutINTEL">;
+def OpTypeAvcImeSingleReferenceStreaminINTEL: Op<5709, (outs TYPE:$res), (ins), "$res = OpTypeAvcImeSingleReferenceStreaminINTEL">;
+def OpTypeAvcImeDualReferenceStreaminINTEL: Op<5710, (outs TYPE:$res), (ins), "$res = OpTypeAvcImeDualReferenceStreaminINTEL">;
+def OpTypeAvcRefResultINTEL: Op<5711, (outs TYPE:$res), (ins), "$res = OpTypeAvcRefResultINTEL">;
+def OpTypeAvcSicResultINTEL: Op<5712, (outs TYPE:$res), (ins), "$res = OpTypeAvcSicResultINTEL">;
// 3.42.7 Constant-Creation Instructions
multiclass IntFPImm<bits<16> opCode, string name> {
@@ -853,6 +866,222 @@ def OpSubgroupImageMediaBlockReadINTEL: Op<5580, (outs ID:$res), (ins TYPE:$type
def OpSubgroupImageMediaBlockWriteINTEL: Op<5581, (outs), (ins ID:$image, ID:$coordinate, ID:$width, ID:$height, ID:$data),
"OpSubgroupImageMediaBlockWriteINTEL $image $coordinate $width $height $data">;
+//SPV_INTEL_device_side_avc_motion_estimation
+def OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL: Op<5713, (outs ID:$res), (ins TYPE:$type, ID:$slicetype, ID:$qp),
+ "$res = OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL $type $slicetype $qp">;
+def OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL: Op<5714, (outs ID:$res), (ins TYPE:$type, ID:$rbp, ID:$payload),
+ "$res = OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL $type $rbp $payload">;
+def OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL: Op<5715, (outs ID:$res), (ins TYPE:$type, ID:$slicetype, ID:$qp),
+ "$res = OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL $type $slicetype $qp">;
+def OpSubgroupAvcMceSetInterShapePenaltyINTEL: Op<5716, (outs ID:$res), (ins TYPE:$type, ID:$pickedshapepenalty, ID:$payload),
+ "$res = OpSubgroupAvcMceSetInterShapePenaltyINTEL $type $pickedshapepenalty $payload">;
+def OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL: Op<5717, (outs ID:$res), (ins TYPE:$type, ID:$slicetype, ID:$qp),
+ "$res = OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL $type $slicetype $qp">;
+def OpSubgroupAvcMceSetInterDirectionPenaltyINTEL: Op<5718, (outs ID:$res), (ins TYPE:$type, ID:$directioncost, ID:$payload),
+ "$res = OpSubgroupAvcMceSetInterDirectionPenaltyINTEL $type $directioncost $payload">;
+def OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL: Op<5719, (outs ID:$res), (ins TYPE:$type, ID:$slicetype, ID:$qp),
+ "$res = OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL $type $slicetype $qp">;
+def OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL: Op<5720, (outs ID:$res), (ins TYPE:$type, ID:$slicetype, ID:$qp),
+ "$res = OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL $type $slicetype $qp">;
+def OpSubgroupAvcMceGetDefaultHighPenaltyCostTableINTEL: Op<5721, (outs ID:$res), (ins TYPE:$type),
+ "$res = OpSubgroupAvcMceGetDefaultHighPenaltyCostTableINTEL $type">;
+def OpSubgroupAvcMceGetDefaultMediumPenaltyCostTableINTEL: Op<5722, (outs ID:$res), (ins TYPE:$type),
+ "$res = OpSubgroupAvcMceGetDefaultMediumPenaltyCostTableINTEL $type">;
+def OpSubgroupAvcMceGetDefaultLowPenaltyCostTableINTEL: Op<5723, (outs ID:$res), (ins TYPE:$type),
+ "$res = OpSubgroupAvcMceGetDefaultLowPenaltyCostTableINTEL $type">;
+def OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL: Op<5724, (outs ID:$res), (ins TYPE:$type, ID:$pccd, ID:$pct, ID:$cp, ID:$payload),
+ "$res = OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL $type $pccd $pct $cp $payload">;
+def OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL: Op<5725, (outs ID:$res), (ins TYPE:$type, ID:$slicetype, ID:$qp),
+ "$res = OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL $type $slicetype $qp">;
+def OpSubgroupAvcMceGetDefaultNonDcLumaIntraPenaltyINTEL: Op<5726, (outs ID:$res), (ins TYPE:$type),
+ "$res = OpSubgroupAvcMceGetDefaultNonDcLumaIntraPenaltyINTEL $type">;
+def OpSubgroupAvcMceGetDefaultIntraChromaModeBasePenaltyINTEL: Op<5727, (outs ID:$res), (ins TYPE:$type),
+ "$res = OpSubgroupAvcMceGetDefaultIntraChromaModeBasePenaltyINTEL $type">;
+def OpSubgroupAvcMceSetAcOnlyHaarINTEL: Op<5728, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceSetAcOnlyHaarINTEL $type $payload">;
+def OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL: Op<5729, (outs ID:$res), (ins TYPE:$type,ID:$sfp, ID:$payload),
+ "$res = OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL $type $sfp $payload">;
+def OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL: Op<5730, (outs ID:$res), (ins TYPE:$type,ID:$rfp, ID:$payload),
+ "$res = OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL $type $rfp $payload">;
+def OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL: Op<5731, (outs ID:$res), (ins TYPE:$type, ID:$brfp, ID:$frfp, ID:$payload),
+ "$res = OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL $type $frfp $brfp $payload">;
+def OpSubgroupAvcMceConvertToImePayloadINTEL: Op<5732, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceConvertToImePayloadINTEL $type $payload">;
+def OpSubgroupAvcMceConvertToImeResultINTEL: Op<5733, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceConvertToImeResultINTEL $type $payload">;
+def OpSubgroupAvcMceConvertToRefPayloadINTEL: Op<5734, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceConvertToRefPayloadINTEL $type $payload">;
+def OpSubgroupAvcMceConvertToRefResultINTEL: Op<5735, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceConvertToRefResultINTEL $type $payload">;
+def OpSubgroupAvcMceConvertToSicPayloadINTEL: Op<5736, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceConvertToSicPayloadINTEL $type $payload">;
+def OpSubgroupAvcMceConvertToSicResultINTEL: Op<5737, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceConvertToSicResultINTEL $type $payload">;
+def OpSubgroupAvcMceGetMotionVectorsINTEL: Op<5738, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetMotionVectorsINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterDistortionsINTEL: Op<5739, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterDistortionsINTEL $type $payload">;
+def OpSubgroupAvcMceGetBestInterDistortionsINTEL: Op<5740, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetBestInterDistortionsINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterMajorShapeINTEL: Op<5741, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterMajorShapeINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterMinorShapeINTEL: Op<5742, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterMinorShapeINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterDirectionsINTEL: Op<5743, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterDirectionsINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterMotionVectorCountINTEL: Op<5744, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterMotionVectorCountINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterReferenceIdsINTEL: Op<5745, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterReferenceIdsINTEL $type $payload">;
+def OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL: Op<5746, (outs ID:$res), (ins TYPE:$type, ID:$prid, ID:$prpfp, ID:$payload),
+ "$res = OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL $type $prid $prpfp $payload">;
+
+def OpVmeImageINTEL: Op<5699, (outs ID:$res), (ins TYPE:$type, ID:$imgtype, ID:$sampler),
+ "$res = OpVmeImageINTEL $type $imgtype $sampler">;
+
+def OpSubgroupAvcImeInitializeINTEL: Op<5747, (outs ID:$res), (ins TYPE:$type, ID:$srccoord, ID:$partitionmask, ID:$SADadj),
+ "$res = OpSubgroupAvcImeInitializeINTEL $type $srccoord $partitionmask $SADadj">;
+def OpSubgroupAvcImeSetSingleReferenceINTEL: Op<5748, (outs ID:$res), (ins TYPE:$type, ID:$refoffset, ID:$swc, ID:$payload),
+ "$res = OpSubgroupAvcImeSetSingleReferenceINTEL $type $refoffset $swc $payload">;
+def OpSubgroupAvcImeSetDualReferenceINTEL: Op<5749, (outs ID:$res), (ins TYPE:$type, ID:$brefoffset, ID:$frefoffset, ID:$swc, ID:$payload),
+ "$res = OpSubgroupAvcImeSetDualReferenceINTEL $type $brefoffset $frefoffset $swc $payload">;
+def OpSubgroupAvcImeRefWindowSizeINTEL: Op<5750, (outs ID:$res), (ins TYPE:$type, ID:$swc, ID:$dualref),
+ "$res = OpSubgroupAvcImeRefWindowSizeINTEL $type $swc $dualref">;
+def OpSubgroupAvcImeAdjustRefOffsetINTEL: Op<5751, (outs ID:$res), (ins TYPE:$type, ID:$refoffset, ID:$srccoord, ID:$rws, ID:$imagesize),
+ "$res = OpSubgroupAvcImeAdjustRefOffsetINTEL $type $refoffset $srccoord $rws $imagesize">;
+def OpSubgroupAvcImeConvertToMcePayloadINTEL: Op<5752, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeConvertToMcePayloadINTEL $type $payload">;
+def OpSubgroupAvcImeSetMaxMotionVectorCountINTEL: Op<5753, (outs ID:$res), (ins TYPE:$type, ID:$maxmv, ID:$payload),
+ "$res = OpSubgroupAvcImeSetMaxMotionVectorCountINTEL $type $maxmv $payload">;
+def OpSubgroupAvcImeSetUnidirectionalMixDisableINTEL: Op<5754, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeSetUnidirectionalMixDisableINTEL $type $payload">;
+def OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL: Op<5755, (outs ID:$res), (ins TYPE:$type, ID:$threshold, ID:$payload),
+ "$res = OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL $type $threshold $payload">;
+def OpSubgroupAvcImeSetWeightedSadINTEL: Op<5756, (outs ID:$res), (ins TYPE:$type, ID:$psw, ID:$payload),
+ "$res = OpSubgroupAvcImeSetWeightedSadINTEL $type $psw $payload">;
+def OpSubgroupAvcImeEvaluateWithSingleReferenceINTEL: Op<5757, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$refimg, ID:$payload),
+ "$res = OpSubgroupAvcImeEvaluateWithSingleReferenceINTEL $type $srcimg $refimg $payload">;
+def OpSubgroupAvcImeEvaluateWithDualReferenceINTEL: Op<5758, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$frefimg, ID:$brefimg, ID:$payload),
+ "$res = OpSubgroupAvcImeEvaluateWithDualReferenceINTEL $type $srcimg $frefimg $brefimg $payload">;
+def OpSubgroupAvcImeEvaluateWithSingleReferenceStreamoutINTEL: Op<5761, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$refimg, ID:$payload),
+ "$res = OpSubgroupAvcImeEvaluateWithSingleReferenceStreamoutINTEL $type $srcimg $refimg $payload">;
+def OpSubgroupAvcImeEvaluateWithDualReferenceStreamoutINTEL: Op<5762, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$frefimg, ID:$brefimg, ID:$payload),
+ "$res = OpSubgroupAvcImeEvaluateWithDualReferenceStreamoutINTEL $type $srcimg $frefimg $brefimg $payload">;
+def OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminINTEL: Op<5759, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$refimg, ID:$payload, ID:$sc),
+ "$res = OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminINTEL $type $srcimg $refimg $payload $sc">;
+def OpSubgroupAvcImeEvaluateWithDualReferenceStreaminINTEL: Op<5760, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$frefimg, ID:$brefimg, ID:$payload, ID:$sc),
+ "$res = OpSubgroupAvcImeEvaluateWithDualReferenceStreaminINTEL $type $srcimg $frefimg $brefimg $payload $sc">;
+def OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminoutINTEL: Op<5763, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$refimg, ID:$payload, ID:$sc),
+ "$res = OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminoutINTEL $type $srcimg $refimg $payload $sc">;
+def OpSubgroupAvcImeEvaluateWithDualReferenceStreaminoutINTEL: Op<5764, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$frefimg, ID:$brefimg, ID:$payload, ID:$sc),
+ "$res = OpSubgroupAvcImeEvaluateWithDualReferenceStreaminoutINTEL $type $srcimg $frefimg $brefimg $payload $sc">;
+def OpSubgroupAvcImeConvertToMceResultINTEL: Op<5765, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeConvertToMceResultINTEL $type $payload">;
+def OpSubgroupAvcImeGetSingleReferenceStreaminINTEL: Op<5766, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeGetSingleReferenceStreaminINTEL $type $payload">;
+def OpSubgroupAvcImeGetDualReferenceStreaminINTEL: Op<5767, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeGetDualReferenceStreaminINTEL $type $payload">;
+def OpSubgroupAvcImeStripSingleReferenceStreamoutINTEL: Op<5768, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeStripSingleReferenceStreamoutINTEL $type $payload">;
+def OpSubgroupAvcImeStripDualReferenceStreamoutINTEL: Op<5769, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeStripDualReferenceStreamoutINTEL $type $payload">;
+def OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL: Op<5770, (outs ID:$res), (ins TYPE:$type, ID:$payload, ID:$majshape),
+ "$res = OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL $type $payload $majshape">;
+def OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL: Op<5771, (outs ID:$res), (ins TYPE:$type, ID:$payload, ID:$majshape),
+ "$res = OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL $type $payload $majshape">;
+def OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL: Op<5772, (outs ID:$res), (ins TYPE:$type, ID:$payload, ID:$majshape),
+ "$res = OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL $type $payload $majshape">;
+def OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL: Op<5773, (outs ID:$res), (ins TYPE:$type, ID:$payload, ID:$majshape, ID:$dir),
+ "$res = OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL $type $payload $majshape $dir">;
+def OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL: Op<5774, (outs ID:$res), (ins TYPE:$type, ID:$payload, ID:$majshape, ID:$dir),
+ "$res = OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL $type $payload $majshape $dir">;
+def OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL: Op<5775, (outs ID:$res), (ins TYPE:$type, ID:$payload, ID:$majshape, ID:$dir),
+ "$res = OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL $type $payload $majshape $dir">;
+def OpSubgroupAvcImeGetBorderReachedINTEL: Op<5776, (outs ID:$res), (ins TYPE:$type, ID:$imgsel, ID:$payload),
+ "$res = OpSubgroupAvcImeGetBorderReachedINTEL $type $imgsel $payload">;
+def OpSubgroupAvcImeGetTruncatedSearchIndicationINTEL: Op<5777, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeGetTruncatedSearchIndicationINTEL $type $payload">;
+def OpSubgroupAvcImeGetUnidirectionalEarlySearchTerminationINTEL: Op<5778, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeGetUnidirectionalEarlySearchTerminationINTEL $type $payload">;
+def OpSubgroupAvcImeGetWeightingPatternMinimumMotionVectorINTEL: Op<5779, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeGetWeightingPatternMinimumMotionVectorINTEL $type $payload">;
+def OpSubgroupAvcImeGetWeightingPatternMinimumDistortionINTEL: Op<5780, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcImeGetWeightingPatternMinimumDistortionINTEL $type $payload">;
+
+def OpSubgroupAvcFmeInitializeINTEL: Op<5781, (outs ID:$res), (ins TYPE:$type, ID:$srccoord, ID:$mv, ID:$majshape, ID:$minorshape, ID:$dir, ID:$pixres, ID:$sadadj),
+ "$res = OpSubgroupAvcFmeInitializeINTEL $type $srccoord $mv $majshape $minorshape $dir $pixres $sadadj">;
+def OpSubgroupAvcBmeInitializeINTEL: Op<5782, (outs ID:$res), (ins TYPE:$type, ID:$srccoord, ID:$mv, ID:$majshape, ID:$minorshape, ID:$dir, ID:$pixres, ID:$bidirwt, ID:$sadadj),
+ "$res = OpSubgroupAvcBmeInitializeINTEL $type $srccoord $mv $majshape $minorshape $dir $pixres $bidirwt $sadadj">;
+def OpSubgroupAvcRefConvertToMcePayloadINTEL: Op<5783, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcRefConvertToMcePayloadINTEL $type $payload">;
+def OpSubgroupAvcRefSetBidirectionalMixDisableINTEL: Op<5784, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcRefSetBidirectionalMixDisableINTEL $type $payload">;
+def OpSubgroupAvcRefSetBilinearFilterEnableINTEL: Op<5785, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcRefSetBilinearFilterEnableINTEL $type $payload">;
+def OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL: Op<5786, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$refimg, ID:$payload),
+ "$res = OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL $type $srcimg $refimg $payload">;
+def OpSubgroupAvcRefEvaluateWithDualReferenceINTEL: Op<5787, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$frefimg, ID:$brefimg, ID:$payload),
+ "$res = OpSubgroupAvcRefEvaluateWithDualReferenceINTEL $type $srcimg $frefimg $brefimg $payload">;
+def OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL: Op<5788, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$pri, ID:$payload),
+ "$res = OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL $type $srcimg $pri $payload">;
+def OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL: Op<5789, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$pri, ID:$prfp, ID:$payload),
+ "$res = OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL $type $srcimg $pri $prfp $payload">;
+def OpSubgroupAvcRefConvertToMceResultINTEL: Op<5790, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcRefConvertToMceResultINTEL $type $payload">;
+
+def OpSubgroupAvcSicInitializeINTEL: Op<5791, (outs ID:$res), (ins TYPE:$type, ID:$srccoord),
+ "$res = OpSubgroupAvcSicInitializeINTEL $type $srccoord">;
+def OpSubgroupAvcSicConfigureSkcINTEL: Op<5792, (outs ID:$res), (ins TYPE:$type, ID:$sbpt, ID:$smvm, ID:$mv, ID:$bw, ID:$sadadj, ID:$payload),
+ "$res = OpSubgroupAvcSicConfigureSkcINTEL $type $sbpt $smvm $mv $bw $sadadj $payload">;
+def OpSubgroupAvcSicConfigureIpeLumaINTEL: Op<5793, (outs ID:$res), (ins TYPE:$type, ID:$lipm, ID:$na, ID:$lelp, ID:$ulclp, ID:$uelp, ID:$urelp, ID:$sadadj, ID:$payload),
+ "$res = OpSubgroupAvcSicConfigureIpeLumaINTEL $type $lipm $na $lelp $ulclp $uelp $urelp $sadadj $payload">;
+def OpSubgroupAvcSicConfigureIpeLumaChromaINTEL: Op<5794, (outs ID:$res), (ins TYPE:$type, ID:$lipm, ID:$ina, ID:$lelp, ID:$ulclp, ID:$uelp, ID:$urelp, ID:$lecp, ID:$ulccp, ID:$uecp, ID:$sadadj, ID:$payload),
+ "$res = OpSubgroupAvcSicConfigureIpeLumaChromaINTEL $type $lipm $ina $lelp $ulclp $uelp $urelp $lecp $ulccp $uecp $sadadj $payload">;
+def OpSubgroupAvcSicGetMotionVectorMaskINTEL: Op<5776, (outs ID:$res), (ins TYPE:$type, ID:$sbpt, ID:$payload),
+ "$res = OpSubgroupAvcSicGetMotionVectorMaskINTEL $type $sbpt $payload">;
+def OpSubgroupAvcSicConvertToMcePayloadINTEL: Op<5796, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicConvertToMcePayloadINTEL $type $payload">;
+def OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL: Op<5797, (outs ID:$res), (ins TYPE:$type, ID:$psp, ID:$payload),
+ "$res = OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL $type $psp $payload">;
+def OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL: Op<5798, (outs ID:$res), (ins TYPE:$type, ID:$lmp, ID:$lpnm, ID:$lpndp, ID:$payload),
+ "$res = OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL $type $lmp $lpnm $lpndp $payload">;
+def OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL: Op<5799, (outs ID:$res), (ins TYPE:$type,ID:$cmbp, ID:$payload),
+ "$res = OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL $type $cmbp $payload">;
+def OpSubgroupAvcSicSetBilinearFilterEnableINTEL: Op<5800, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicSetBilinearFilterEnableINTEL $type $payload">;
+def OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL: Op<5801, (outs ID:$res), (ins TYPE:$type, ID:$psc, ID:$payload),
+ "$res = OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL $type $psc $payload">;
+def OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL: Op<5802, (outs ID:$res), (ins TYPE:$type, ID:$bbst, ID:$payload),
+ "$res = OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL $type $bbst $payload">;
+def OpSubgroupAvcSicEvaluateIpeINTEL: Op<5803, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$payload),
+ "$res = OpSubgroupAvcSicEvaluateIpeINTEL $type $srcimg $payload">;
+def OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL: Op<5804, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID: $refimg, ID:$payload),
+ "$res = OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL $type $srcimg $refimg $payload">;
+def OpSubgroupAvcSicEvaluateWithDualReferenceINTEL: Op<5805, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$frefimg, ID:$brefimg, ID:$payload),
+ "$res = OpSubgroupAvcSicEvaluateWithDualReferenceINTEL $type $srcimg $frefimg $brefimg $payload">;
+def OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL: Op<5806, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$pri, ID:$payload),
+ "$res = OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL $type $srcimg $pri $payload">;
+def OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL: Op<5807, (outs ID:$res), (ins TYPE:$type, ID:$srcimg, ID:$pri, ID:$prfp, ID:$payload),
+ "$res = OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL $type $srcimg $pri $prfp $payload">;
+def OpSubgroupAvcSicConvertToMceResultINTEL: Op<5808, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicConvertToMceResultINTEL $type $payload">;
+def OpSubgroupAvcSicGetIpeLumaShapeINTEL: Op<5809, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetIpeLumaShapeINTEL $type $payload">;
+def OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL: Op<5810, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL $type $payload">;
+def OpSubgroupAvcSicGetBestIpeChromaDistortionINTEL: Op<5811, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetBestIpeChromaDistortionINTEL $type $payload">;
+def OpSubgroupAvcSicGetPackedIpeLumaModesINTEL: Op<5812, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetPackedIpeLumaModesINTEL $type $payload">;
+def OpSubgroupAvcSicGetIpeChromaModeINTEL: Op<5813, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetIpeChromaModeINTEL $type $payload">;
+def OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL: Op<5814, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL $type $payload">;
+def OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL: Op<5815, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL $type $payload">;
+def OpSubgroupAvcSicGetInterRawSadsINTEL: Op<5816, (outs ID:$res), (ins TYPE:$type, ID:$payload),
+ "$res = OpSubgroupAvcSicGetInterRawSadsINTEL $type $payload">;
+
// - SPV_KHR_uniform_group_instructions
def OpGroupIMulKHR: Op<6401, (outs ID:$res), (ins TYPE:$type, ID:$scope, i32imm:$groupOp, ID:$value),
"$res = OpGroupIMulKHR $type $scope $groupOp $value">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index b1e5e4328cd32..00307d822f0fb 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -1810,6 +1810,37 @@ void addInstrRequirements(const MachineInstr &MI,
Reqs.addCapability(SPIRV::Capability::TernaryBitwiseFunctionINTEL);
break;
}
+ case SPIRV::OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL:
+ case SPIRV::OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL:
+ case SPIRV::OpSubgroupAvcMceGetDefaultNonDcLumaIntraPenaltyINTEL:
+ case SPIRV::OpSubgroupAvcSicConfigureIpeLumaINTEL:
+ case SPIRV::OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL:
+ case SPIRV::OpSubgroupAvcSicEvaluateIpeINTEL:
+ case SPIRV::OpSubgroupAvcSicGetIpeLumaShapeINTEL:
+ case SPIRV::OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL:
+ case SPIRV::OpSubgroupAvcSicGetPackedIpeLumaModesINTEL:
+ case SPIRV::OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL:
+ case SPIRV::OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL:
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ Reqs.addExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ Reqs.addCapability(
+ llvm::SPIRV::Capability::SubgroupAvcMotionEstimationIntraINTEL);
+ break;
+ }
+ case SPIRV::OpSubgroupAvcMceGetDefaultIntraChromaModeBasePenaltyINTEL:
+ case SPIRV::OpSubgroupAvcSicConfigureIpeLumaChromaINTEL:
+ case SPIRV::OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL:
+ case SPIRV::OpSubgroupAvcSicGetIpeChromaModeINTEL:
+ if (ST.canUseExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation)) {
+ Reqs.addExtension(
+ SPIRV::Extension::SPV_INTEL_device_side_avc_motion_estimation);
+ Reqs.addCapability(
+ llvm::SPIRV::Capability::SubgroupAvcMotionEstimationChromaINTEL);
+ }
+ break;
default:
break;
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 3fcff3dd8f553..80faf70ac0a82 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -104,6 +104,10 @@ addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR,
SrcMI->setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull));
SrcMI->addOperand(MachineOperand::CreateReg(
GR->getSPIRVTypeID(ExtType), false));
+ //check in machine verifier fails in other cases
+ SrcMI->getOperand(0);
+ MRI.setRegClass(SrcMI->getOperand(0).getReg(),
+ &SPIRV::iIDRegClass);
}
}
} else {
@@ -1074,7 +1078,6 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
insertSpirvDecorations(MF, GR, MIB);
insertInlineAsm(MF, GR, ST, MIB);
selectOpBitcasts(MF, GR, MIB);
-
return true;
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
index 628688d83a314..a29c3fcb4f440 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
@@ -94,7 +94,6 @@ static bool lowerIntrinsicToFunction(IntrinsicInst *Intrinsic) {
if (auto *MSI = dyn_cast<MemSetInst>(Intrinsic))
if (isa<Constant>(MSI->getValue()) && isa<ConstantInt>(MSI->getLength()))
return false; // It is handled later using OpCopyMemorySized.
-
Module *M = Intrinsic->getModule();
std::string FuncName = lowerLLVMIntrinsicName(Intrinsic);
if (Intrinsic->isVolatile())
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index 0db8a37f8683c..f2fb4fdbc2447 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -314,6 +314,7 @@ defm SPV_INTEL_long_composites : ExtensionOperand<117>;
defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
defm SPV_INTEL_fp_max_error : ExtensionOperand<119>;
defm SPV_INTEL_ternary_bitwise_function : ExtensionOperand<120>;
+defm SPV_INTEL_device_side_avc_motion_estimation: ExtensionOperand<121>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -457,9 +458,9 @@ defm SubgroupShuffleINTEL : CapabilityOperand<5568, 0, 0, [SPV_INTEL_subgroups],
defm SubgroupBufferBlockIOINTEL : CapabilityOperand<5569, 0, 0, [SPV_INTEL_subgroups], []>;
defm SubgroupImageBlockIOINTEL : CapabilityOperand<5570, 0, 0, [SPV_INTEL_subgroups], []>;
defm SubgroupImageMediaBlockIOINTEL : CapabilityOperand<5579, 0, 0, [SPV_INTEL_media_block_io], []>;
-defm SubgroupAvcMotionEstimationINTEL : CapabilityOperand<5696, 0, 0, [], []>;
-defm SubgroupAvcMotionEstimationIntraINTEL : CapabilityOperand<5697, 0, 0, [], []>;
-defm SubgroupAvcMotionEstimationChromaINTEL : CapabilityOperand<5698, 0, 0, [], []>;
+defm SubgroupAvcMotionEstimationINTEL : CapabilityOperand<5696, 0, 0, [SPV_INTEL_device_side_avc_motion_estimation], []>;
+defm SubgroupAvcMotionEstimationIntraINTEL : CapabilityOperand<5697, 0, 0, [SPV_INTEL_device_side_avc_motion_estimation], []>;
+defm SubgroupAvcMotionEstimationChromaINTEL : CapabilityOperand<5698, 0, 0, [SPV_INTEL_device_side_avc_motion_estimation], []>;
defm GroupNonUniformPartitionedNV : CapabilityOperand<5297, 0, 0, [], []>;
defm VulkanMemoryModelKHR : CapabilityOperand<5345, 0, 0, [], []>;
defm VulkanMemoryModelDeviceScopeKHR : CapabilityOperand<5346, 0, 0, [], []>;
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
new file mode 100644
index 0000000000000..c46ff83a3e71e
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
@@ -0,0 +1,193 @@
+// RUN: clang -cc1 -O1 -triple spirv64-unknown-unknown -cl-std=CL2.0 -finclude-default-header -emit-llvm %s -o %t.ll
+// RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %t.ll -o - | FileCheck %s
+void foo(intel_sub_group_avc_ime_payload_t ime_payload,
+ intel_sub_group_avc_ime_result_single_reference_streamout_t sstreamout,
+ intel_sub_group_avc_ime_result_dual_reference_streamout_t dstreamout,
+ intel_sub_group_avc_ime_result_t ime_result,
+ intel_sub_group_avc_mce_result_t mce_result,
+ intel_sub_group_avc_ref_payload_t ref_payload,
+ intel_sub_group_avc_sic_payload_t sic_payload,
+ intel_sub_group_avc_sic_result_t sic_result,
+ intel_sub_group_avc_mce_payload_t mce_payload) {
+ intel_sub_group_avc_mce_get_default_inter_base_multi_reference_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_shape_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_intra_luma_shape_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_motion_vector_cost_table(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_direction_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_intra_luma_mode_penalty(0, 0);
+
+ intel_sub_group_avc_ime_initialize(0, 0, 0);
+ intel_sub_group_avc_ime_set_single_reference(0, 0, ime_payload);
+ intel_sub_group_avc_ime_set_dual_reference(0, 0, 0, ime_payload);
+ intel_sub_group_avc_ime_ref_window_size(0, 0);
+ intel_sub_group_avc_ime_ref_window_size(0, 0);
+ intel_sub_group_avc_ime_adjust_ref_offset(0, 0, 0, 0);
+ intel_sub_group_avc_ime_set_max_motion_vector_count(0, ime_payload);
+
+ intel_sub_group_avc_ime_get_single_reference_streamin(sstreamout);
+
+ intel_sub_group_avc_ime_get_dual_reference_streamin(dstreamout);
+
+ intel_sub_group_avc_ime_get_border_reached(0i, ime_result);
+
+ intel_sub_group_avc_ime_get_streamout_major_shape_distortions(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_distortions(dstreamout, 0, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_motion_vectors(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_motion_vectors(dstreamout, 0, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_reference_ids(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_reference_ids(dstreamout, 0, 0);
+
+ intel_sub_group_avc_ime_set_dual_reference(0, 0, 0, ime_payload);
+ intel_sub_group_avc_ime_set_weighted_sad(0, ime_payload);
+
+ intel_sub_group_avc_ime_set_early_search_termination_threshold(0, ime_payload);
+
+ intel_sub_group_avc_fme_initialize(0, 0, 0, 0, 0, 0, 0);
+ intel_sub_group_avc_bme_initialize(0, 0, 0, 0, 0, 0, 0, 0);
+
+ intel_sub_group_avc_ref_set_bidirectional_mix_disable(ref_payload);
+
+ intel_sub_group_avc_sic_initialize(0);
+ intel_sub_group_avc_sic_configure_ipe(0, 0, 0, 0, 0, 0, 0, sic_payload);
+ intel_sub_group_avc_sic_configure_ipe(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, sic_payload);
+
+ intel_sub_group_avc_sic_configure_skc(0, 0, 0, 0, 0, sic_payload);
+
+ intel_sub_group_avc_sic_set_skc_forward_transform_enable(0, sic_payload);
+ intel_sub_group_avc_sic_set_block_based_raw_skip_sad(0, sic_payload);
+ intel_sub_group_avc_sic_set_intra_luma_shape_penalty(0, sic_payload);
+ intel_sub_group_avc_sic_set_intra_luma_mode_cost_function(0, 0, 0,
+ sic_payload);
+ intel_sub_group_avc_sic_set_intra_chroma_mode_cost_function(0, sic_payload);
+
+ intel_sub_group_avc_sic_get_best_ipe_luma_distortion(sic_result);
+ intel_sub_group_avc_sic_get_motion_vector_mask(0, 0);
+
+ intel_sub_group_avc_mce_set_source_interlaced_field_polarity(0, mce_payload);
+ intel_sub_group_avc_mce_set_single_reference_interlaced_field_polarity(
+ 0, mce_payload);
+ intel_sub_group_avc_mce_set_dual_reference_interlaced_field_polarities(
+ 0, 0, mce_payload);
+ intel_sub_group_avc_mce_set_inter_base_multi_reference_penalty(0,
+ mce_payload);
+ intel_sub_group_avc_mce_set_inter_shape_penalty(0, mce_payload);
+ intel_sub_group_avc_mce_set_inter_direction_penalty(0, mce_payload);
+ intel_sub_group_avc_mce_set_motion_vector_cost_function(0, 0, 0, mce_payload);
+
+ intel_sub_group_avc_mce_get_inter_reference_interlaced_field_polarities(
+ 0, 0, mce_result);
+}
+
+// CHECK-DAG: OpCapability Groups
+// CHECK-DAG: OpCapability SubgroupAvcMotionEstimationINTEL
+// CHECK-DAG: OpCapability SubgroupAvcMotionEstimationIntraINTEL
+// CHECK-DAG: OpCapability SubgroupAvcMotionEstimationChromaINTEL
+// CHECK-DAG: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+
+// CHECK: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+// CHECK: %[[#ImeSRefOutTy:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+// CHECK: %[[#ImeDRefOutTy:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+// CHECK: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+// CHECK: %[[#MceResultTy:]] = OpTypeAvcMceResultINTEL
+// CHECK: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+// CHECK: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+// CHECK: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+// CHECK: %[[#McePayloadTy:]] = OpTypeAvcMcePayloadINTEL
+// CHECK: %[[#ImeSRefInTy:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+// CHECK: %[[#ImeDRefInTy:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+
+// CHECK: %[[#ImePayload:]] = OpFunctionParameter %[[#ImePayloadTy]]
+// CHECK: %[[#ImeSRefOut:]] = OpFunctionParameter %[[#ImeSRefOutTy]]
+// CHECK: %[[#ImeDRefOut:]] = OpFunctionParameter %[[#ImeDRefOutTy]]
+// CHECK: %[[#ImeResult:]] = OpFunctionParameter %[[#ImeResultTy]]
+// CHECK: %[[#MceResult:]] = OpFunctionParameter %[[#MceResultTy]]
+// CHECK: %[[#RefPayload:]] = OpFunctionParameter %[[#RefPayloadTy]]
+// CHECK: %[[#SicPayload:]] = OpFunctionParameter %[[#SicPayloadTy]]
+// CHECK: %[[#SicResult:]] = OpFunctionParameter %[[#SicResultTy]]
+// CHECK: %[[#McePayload:]] = OpFunctionParameter %[[#McePayloadTy]]
+
+
+// CHECK: OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL
+
+// CHECK: OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL
+
+// CHECK: OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL
+
+// CHECK: OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL
+
+// CHECK: OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL
+
+// CHECK: OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL
+
+
+// CHECK: OpSubgroupAvcImeInitializeINTEL %[[#ImePayloadTy]]
+
+// CHECK: OpSubgroupAvcImeSetSingleReferenceINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+
+// CHECK: OpSubgroupAvcImeSetDualReferenceINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+
+// CHECK: OpSubgroupAvcImeRefWindowSizeINTEL
+
+// CHECK: OpSubgroupAvcImeRefWindowSizeINTEL
+
+// CHECK: OpSubgroupAvcImeAdjustRefOffsetINTEL
+
+// CHECK: OpSubgroupAvcImeSetMaxMotionVectorCountINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+
+// CHECK: OpSubgroupAvcImeGetSingleReferenceStreaminINTEL %[[#ImeSRefInTy]]{{.*}}%[[#ImeSRefOut]]
+
+// CHECK: OpSubgroupAvcImeGetDualReferenceStreaminINTEL %[[#ImeDRefInTy]]{{.*}}%[[#ImeDRefOut]]
+
+// CHECK: OpSubgroupAvcImeGetBorderReachedINTEL {{.*}} %[[#ImeResult]]
+
+// CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL {{.*}} %[[#ImeSRefOut]]
+// CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL {{.*}} %[[#ImeDRefOut]]
+// CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL {{.*}} %[[#ImeSRefOut]]
+// CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL {{.*}} %[[#ImeDRefOut]]
+// CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL {{.*}} %[[#ImeSRefOut]]
+// CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL {{.*}} %[[#ImeDRefOut]]
+
+
+// CHECK: OpSubgroupAvcImeSetDualReferenceINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+
+// CHECK: OpSubgroupAvcImeSetWeightedSadINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+
+// CHECK: OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL %[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+
+// CHECK: OpSubgroupAvcFmeInitializeINTEL %[[#RefPayloadTy]]
+
+// CHECK: OpSubgroupAvcBmeInitializeINTEL %[[#RefPayloadTy]]
+
+
+// CHECK: OpSubgroupAvcRefSetBidirectionalMixDisableINTEL %[[#RefPayloadTy]]{{.*}}%[[#RefPayload]]
+
+
+// CHECK: OpSubgroupAvcSicInitializeINTEL %[[#SicPayloadTy]]
+
+// CHECK: OpSubgroupAvcSicConfigureIpeLumaINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+// CHECK: OpSubgroupAvcSicConfigureIpeLumaChromaINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+
+// CHECK: OpSubgroupAvcSicConfigureSkcINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+
+// CHECK: OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+// CHECK: OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+// CHECK: OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+// CHECK: OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+// CHECK: OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL %[[#SicPayloadTy]] {{.*}} %[[#SicPayload]]
+
+// CHECK: OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL {{.*}} %[[#SicResult]]
+
+// CHECK: OpSubgroupAvcSicGetMotionVectorMaskINTEL
+
+// CHECK: OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+// CHECK: OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+// CHECK: OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+// CHECK: OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+// CHECK: OpSubgroupAvcMceSetInterShapePenaltyINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+// CHECK: OpSubgroupAvcMceSetInterDirectionPenaltyINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+// CHECK: OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL %[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+
+
+// CHECK: OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL {{.*}} %[[#MceResult]]
+
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll
new file mode 100644
index 0000000000000..84e3221c31d45
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll
@@ -0,0 +1,42 @@
+; Source:
+; void __attribute__((overloadable)) intel_sub_group_avc_mce_ime_boo();
+; void foo() {
+; intel_sub_group_avc_mce_ime_boo();
+; }
+
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+
+; Checks that a function with a name started from 'intel_sub_group_avc_' prefix,
+; but which is not a part of 'cl_intel_device_side_avc_motion_estimation'
+; extension specification, is being translated to a regular FunctionCall.
+
+; CHECK: OpName %[[#Name:]] "_Z31intel_sub_group_avc_mce_ime_boo"
+; CHECK: %[[#]] = OpFunctionCall %[[#]] %[[#Name]]
+
+
+; Function Attrs: noinline nounwind optnone
+define spir_func void @foo() #0 {
+entry:
+ call spir_func void @_Z31intel_sub_group_avc_mce_ime_boo()
+ ret void
+}
+
+declare spir_func void @_Z31intel_sub_group_avc_mce_ime_boo() #1
+
+attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.enable.FP_CONTRACT = !{}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!opencl.used.extensions = !{!2}
+!opencl.used.optional.core.features = !{!2}
+!opencl.compiler.options = !{!2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{}
+!3 = !{!"clang version 5.0.1 (cfe/trunk)"}
+
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
new file mode 100644
index 0000000000000..4603cc3adac5d
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
@@ -0,0 +1,101 @@
+; Source:
+;
+; #pragma OPENCL EXTENSION cl_intel_device_side_avc_motion_estimation : enable
+;
+; void foo() {
+; intel_sub_group_avc_mce_payload_t payload_mce; // No literal initializer for mce types
+; intel_sub_group_avc_ime_payload_t payload_ime = CLK_AVC_IME_PAYLOAD_INITIALIZE_INTEL;
+; intel_sub_group_avc_ref_payload_t payload_ref = CLK_AVC_REF_PAYLOAD_INITIALIZE_INTEL;
+; intel_sub_group_avc_sic_payload_t payload_sic = CLK_AVC_SIC_PAYLOAD_INITIALIZE_INTEL;
+;
+; intel_sub_group_avc_mce_result_t result_mce; // No literal initializer for mce types
+; intel_sub_group_avc_ime_result_t result_ime = CLK_AVC_IME_RESULT_INITIALIZE_INTEL;
+; intel_sub_group_avc_ref_result_t result_ref = CLK_AVC_REF_RESULT_INITIALIZE_INTEL;
+; intel_sub_group_avc_sic_result_t result_sic = CLK_AVC_SIC_RESULT_INITIALIZE_INTEL;
+;
+; intel_sub_group_avc_ime_result_single_reference_streamout_t sstreamout = 0x0;
+; intel_sub_group_avc_ime_result_dual_reference_streamout_t dstreamout = 0x0;
+; intel_sub_group_avc_ime_single_reference_streamin_t sstreamin = 0x0;
+; intel_sub_group_avc_ime_dual_reference_streamin_t dstreamin = 0x0;
+; }
+
+; RUN:llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+
+; CHECK: OpCapability Groups
+; CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+; CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+; CHECK: OpTypeAvcMcePayloadINTEL
+; CHECK: %[[#IME_PAYLOAD:]] = OpTypeAvcImePayloadINTEL
+; CHECK: %[[#REF_PAYLOAD:]] = OpTypeAvcRefPayloadINTEL
+; CHECK: %[[#SIC_PAYLOAD:]] = OpTypeAvcSicPayloadINTEL
+; CHECK: OpTypeAvcMceResultINTEL
+; CHECK: %[[#IME_RESULT:]] = OpTypeAvcImeResultINTEL
+; CHECK: %[[#REF_RESULT:]] = OpTypeAvcRefResultINTEL
+; CHECK: %[[#SIC_RESULT:]] = OpTypeAvcSicResultINTEL
+; CHECK: %[[#SSTREAMOUT:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+; CHECK: %[[#DSTREAMOUT:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+; CHECK: %[[#SSTREAMIN:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+; CHECK: %[[#DSTREAMIN:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+
+; //CHECK: %[[#IME_PAYLOAD:]] = OpConstantNull
+; //CHECK: %[[#REF_PAYLOAD:]] = OpConstantNull
+; //CHECK: %[[#SIC_PAYLOAD:]] = OpConstantNull
+; //CHECK: %[[#IME_RESULT:]] = OpConstantNull
+; //CHECK: %[[#REF_RESULT:]] = OpConstantNull
+; //CHECK: %[[#SIC_RESULT:]] = OpConstantNull
+; //CHECK: %[[#SSTREAMOUT:]] = OpConstantNull
+; //CHECK: %[[#DSTREAMOUT:]] = OpConstantNull
+; //CHECK: %[[#SSTREAMIN:]] = OpConstantNull
+; //CHECK: %[[#DSTREAMIN:]] = OpConstantNull
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spirv64-unknown-unknown"
+
+; Function Attrs: noinline nounwind optnone
+define spir_func void @foo() #0 {
+entry:
+
+ %payload_mce = alloca target("spirv.AvcMcePayloadINTEL"), align 4
+ %payload_ime = alloca target("spirv.AvcImePayloadINTEL"), align 4
+ %payload_ref = alloca target("spirv.AvcRefPayloadINTEL"), align 4
+ %payload_sic = alloca target("spirv.AvcSicPayloadINTEL"), align 4
+ %result_mce = alloca target("spirv.AvcMceResultINTEL"), align 4
+ %result_ime = alloca target("spirv.AvcImeResultINTEL"), align 4
+ %result_ref = alloca target("spirv.AvcRefResultINTEL"), align 4
+ %result_sic = alloca target("spirv.AvcSicResultINTEL"), align 4
+ %sstreamout = alloca target("spirv.AvcImeResultSingleReferenceStreamoutINTEL"), align 4
+ %dstreamout = alloca target("spirv.AvcImeResultDualReferenceStreamoutINTEL"), align 4
+ %sstreamin = alloca target("spirv.AvcImeSingleReferenceStreaminINTEL"), align 4
+ %dstreamin = alloca target("spirv.AvcImeDualReferenceStreaminINTEL"), align 4
+ store target("spirv.AvcMcePayloadINTEL") zeroinitializer, ptr %payload_mce, align 4
+ store target("spirv.AvcImePayloadINTEL") zeroinitializer, ptr %payload_ime, align 4
+ store target("spirv.AvcRefPayloadINTEL") zeroinitializer, ptr %payload_ref, align 4
+ store target("spirv.AvcSicPayloadINTEL") zeroinitializer, ptr %payload_sic, align 4
+ store target("spirv.AvcMceResultINTEL") zeroinitializer, ptr %result_mce, align 4
+ store target("spirv.AvcImeResultINTEL") zeroinitializer, ptr %result_ime, align 4
+ store target("spirv.AvcRefResultINTEL") zeroinitializer, ptr %result_ref, align 4
+ store target("spirv.AvcSicResultINTEL") zeroinitializer, ptr %result_sic, align 4
+ store target("spirv.AvcImeResultSingleReferenceStreamoutINTEL") zeroinitializer, ptr %sstreamout, align 4
+ store target("spirv.AvcImeResultDualReferenceStreamoutINTEL") zeroinitializer, ptr %dstreamout, align 4
+ store target("spirv.AvcImeSingleReferenceStreaminINTEL") zeroinitializer, ptr %sstreamin, align 4
+ store target("spirv.AvcImeDualReferenceStreaminINTEL") zeroinitializer, ptr %dstreamin, align 4
+ ret void
+}
+
+attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.enable.FP_CONTRACT = !{}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!opencl.used.extensions = !{!2}
+!opencl.used.optional.core.features = !{!2}
+!opencl.compiler.options = !{!2}
+!llvm.ident = !{!3}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{}
+!3 = !{!"clang version 5.0.1 (cfe/trunk)"}
+
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_vme_image.cl b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_vme_image.cl
new file mode 100644
index 0000000000000..18ad6dfb5e22a
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_vme_image.cl
@@ -0,0 +1,146 @@
+// RUN: clang -cc1 -O1 -triple spirv64-unknown-unknown -cl-std=CL2.0 -finclude-default-header -emit-llvm %s -o %t.ll
+// RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %t.ll -o - | FileCheck %s
+
+#pragma OPENCL EXTENSION cl_intel_device_side_avc_motion_estimation : enable
+
+void foo(__read_only image2d_t src, __read_only image2d_t ref,
+ sampler_t sampler, intel_sub_group_avc_ime_payload_t ime_payload,
+ intel_sub_group_avc_ime_single_reference_streamin_t sstreamin,
+ intel_sub_group_avc_ime_dual_reference_streamin_t dstreamin,
+ intel_sub_group_avc_ref_payload_t ref_payload,
+ intel_sub_group_avc_sic_payload_t sic_payload) {
+ intel_sub_group_avc_ime_evaluate_with_single_reference(src, ref, sampler,
+ ime_payload);
+ intel_sub_group_avc_ime_evaluate_with_dual_reference(src, ref, ref, sampler,
+ ime_payload);
+ intel_sub_group_avc_ime_evaluate_with_single_reference_streamout(
+ src, ref, sampler, ime_payload);
+ intel_sub_group_avc_ime_evaluate_with_dual_reference_streamout(
+ src, ref, ref, sampler, ime_payload);
+ intel_sub_group_avc_ime_evaluate_with_single_reference_streamin(
+ src, ref, sampler, ime_payload, sstreamin);
+ intel_sub_group_avc_ime_evaluate_with_dual_reference_streamin(
+ src, ref, ref, sampler, ime_payload, dstreamin);
+ intel_sub_group_avc_ime_evaluate_with_single_reference_streaminout(
+ src, ref, sampler, ime_payload, sstreamin);
+ intel_sub_group_avc_ime_evaluate_with_dual_reference_streaminout(
+ src, ref, ref, sampler, ime_payload, dstreamin);
+
+ intel_sub_group_avc_ref_evaluate_with_single_reference(src, ref, sampler,
+ ref_payload);
+ intel_sub_group_avc_ref_evaluate_with_dual_reference(src, ref, ref, sampler,
+ ref_payload);
+ intel_sub_group_avc_ref_evaluate_with_multi_reference(src, 0, sampler,
+ ref_payload);
+ intel_sub_group_avc_ref_evaluate_with_multi_reference(src, 0, 0, sampler,
+ ref_payload);
+
+ intel_sub_group_avc_sic_evaluate_with_single_reference(src, ref, sampler,
+ sic_payload);
+ intel_sub_group_avc_sic_evaluate_with_dual_reference(src, ref, ref, sampler,
+ sic_payload);
+ intel_sub_group_avc_sic_evaluate_with_multi_reference(src, 0, sampler,
+ sic_payload);
+ intel_sub_group_avc_sic_evaluate_with_multi_reference(src, 0, 0, sampler,
+ sic_payload);
+ intel_sub_group_avc_sic_evaluate_ipe(src, sampler, sic_payload);
+}
+
+// CHECK: OpCapability Groups
+// CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+
+// CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+// CHECK-DAG: %[[#ImageTy:]] = OpTypeImage
+// CHECK-DAG: %[[#SamplerTy:]] = OpTypeSampler
+// CHECK-DAG: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+// CHECK-DAG: %[[#ImeSRefInTy:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+// CHECK-DAG: %[[#ImeDRefInTy:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+// CHECK-DAG: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+// CHECK-DAG: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+// CHECK-DAG: %[[#VmeImageTy:]] = OpTypeVmeImageINTEL
+// CHECK-DAG: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+// CHECK-DAG: %[[#ImeSRefOutTy:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+// CHECK-DAG: %[[#ImeDRefOutTy:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+// CHECK-DAG: %[[#RefResultTy:]] = OpTypeAvcRefResultINTEL
+// CHECK-DAG: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+
+// CHECK: %[[#SrcImg:]] = OpFunctionParameter %[[#ImageTy]]
+// CHECK: %[[#RefImg:]] = OpFunctionParameter %[[#ImageTy]]
+// CHECK: %[[#Sampler:]] = OpFunctionParameter %[[#SamplerTy]]
+// CHECK: %[[#ImePayload:]] = OpFunctionParameter %[[#ImePayloadTy]]
+// CHECK: %[[#ImeSRefIn:]] = OpFunctionParameter %[[#ImeSRefInTy]]
+// CHECK: %[[#ImeDRefIn:]] = OpFunctionParameter %[[#ImeDRefInTy]]
+// CHECK: %[[#RefPayload:]] = OpFunctionParameter %[[#RefPayloadTy]]
+// CHECK: %[[#SicPayload:]] = OpFunctionParameter %[[#SicPayloadTy]]
+
+// CHECK: %[[#VmeImg0:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg1:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithSingleReferenceINTEL %[[#ImeResultTy]]{{.*}}%[[#VmeImg0]] %[[#VmeImg1]] %[[#ImePayload]]
+
+// CHECK: %[[#VmeImg2:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg3:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg4:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithDualReferenceINTEL %[[#ImeResultTy]]{{.*}}%[[#VmeImg2]] %[[#VmeImg3]] %[[#VmeImg4]] %[[#ImePayload]]
+
+// CHECK: %[[#VmeImg5:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg6:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithSingleReferenceStreamoutINTEL %[[#ImeSRefOutTy]]{{.*}}%[[#VmeImg5]] %[[#VmeImg6]] %[[#ImePayload]]
+
+// CHECK: %[[#VmeImg7:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg8:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg9:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithDualReferenceStreamoutINTEL %[[#ImeDRefOutTy]]{{.*}}%[[#VmeImg7]] %[[#VmeImg8]] %[[#VmeImg9]] %[[#ImePayload]]
+
+// CHECK: %[[#VmeImg10:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg11:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminINTEL %[[#ImeResultTy]]{{.*}}%[[#VmeImg10]] %[[#VmeImg11]] %[[#ImePayload]] %[[#ImeSRefIn]]
+
+// CHECK: %[[#VmeImg12:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg13:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg14:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithDualReferenceStreaminINTEL %[[#ImeResultTy]]{{.*}}%[[#VmeImg12]] %[[#VmeImg13]] %[[#VmeImg14]] %[[#ImePayload]] %[[#ImeDRefIn]]
+
+// CHECK: %[[#VmeImg1:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg2:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithSingleReferenceStreaminoutINTEL %[[#ImeSRefOutTy]]{{.*}}%[[#VmeImg1]] %[[#VmeImg2]] %[[#ImePayload]] %[[#ImeSRefIn]]
+
+// CHECK: %[[#VmeImg1:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg2:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg3:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcImeEvaluateWithDualReferenceStreaminoutINTEL %[[#ImeDRefOutTy]]{{.*}}%[[#VmeImg1]] %[[#VmeImg2]] %[[#VmeImg3]] %[[#ImePayload]] %[[#ImeDRefIn]]
+
+// CHECK: %[[#VmeImg15:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg16:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcRefEvaluateWithSingleReferenceINTEL %[[#RefResultTy]]{{.*}}%[[#VmeImg15]] %[[#VmeImg16]] %[[#RefPayload]]
+
+// CHECK: %[[#VmeImg17:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg18:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg19:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcRefEvaluateWithDualReferenceINTEL %[[#RefResultTy]]{{.*}}%[[#VmeImg17]] %[[#VmeImg18]] %[[#VmeImg19]] %[[#RefPayload]]
+
+
+// CHECK: %[[#VmeImg20:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcRefEvaluateWithMultiReferenceINTEL %[[#RefResultTy]]{{.*}}%[[#VmeImg20]]{{.*}}%[[#RefPayload]]
+
+// CHECK: %[[#VmeImg21:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcRefEvaluateWithMultiReferenceInterlacedINTEL %[[#RefResultTy]]{{.*}}%[[#VmeImg21]]{{.*}}%[[#RefPayload]]
+
+// CHECK: %[[#VmeImg23:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg24:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcSicEvaluateWithSingleReferenceINTEL %[[#SicResultTy]]{{.*}}%[[#VmeImg23]] %[[#VmeImg24]] %[[#SicPayload]]
+
+// CHECK: %[[#VmeImg25:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg26:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: %[[#VmeImg27:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#RefImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcSicEvaluateWithDualReferenceINTEL %[[#SicResultTy]]{{.*}}%[[#VmeImg25]] %[[#VmeImg26]] %[[#VmeImg27]] %[[#SicPayload]]
+
+// CHECK: %[[#VmeImg28:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcSicEvaluateWithMultiReferenceINTEL %[[#SicResultTy]]{{.*}}%[[#VmeImg28]]{{.*}}%[[#SicPayload]]
+
+// CHECK: %[[#VmeImg29:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcSicEvaluateWithMultiReferenceInterlacedINTEL %[[#SicResultTy]]{{.*}}%[[#VmeImg29]]{{.*}}%[[#SicPayload]]
+
+// CHECK: %[[#VmeImg30:]] = OpVmeImageINTEL %[[#VmeImageTy]] %[[#SrcImg]] %[[#Sampler]]
+// CHECK: OpSubgroupAvcSicEvaluateIpeINTEL %[[#SicResultTy]]{{.*}}%[[#VmeImg30]] %[[#SicPayload]]
+
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll
new file mode 100644
index 0000000000000..936d19790f891
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll
@@ -0,0 +1,154 @@
+; Source:
+;
+; #pragma OPENCL EXTENSION cl_intel_device_side_avc_motion_estimation : enable
+; void test(__read_only image2d_t src,
+; __read_only image2d_t ref,
+; sampler_t sampler) {
+;
+; intel_sub_group_avc_ime_payload_t ime_payload;
+; ime_payload = intel_sub_group_avc_ime_set_inter_base_multi_reference_penalty(
+; 0, ime_payload);
+;
+; intel_sub_group_avc_ime_result_t ime_result;
+; intel_sub_group_avc_ime_get_motion_vectors(ime_result);
+;
+; intel_sub_group_avc_ref_payload_t ref_payload;
+; ref_payload = intel_sub_group_avc_ref_set_inter_shape_penalty(0, ref_payload);
+;
+; intel_sub_group_avc_ref_result_t ref_result;
+; intel_sub_group_avc_ref_get_inter_distortions(ref_result);
+;
+; intel_sub_group_avc_sic_payload_t sic_payload;
+; sic_payload = intel_sub_group_avc_sic_set_motion_vector_cost_function(
+; 0, 0, 0, sic_payload);
+;
+; intel_sub_group_avc_sic_result_t sic_result;
+; intel_sub_group_avc_sic_get_inter_distortions(sic_result);
+; }
+
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+
+
+; The test checks that 'cl_intel_device_side_avc_motion_estimation' wrapper built-ins correctly
+; translated to 'SPV_INTEL_device_side_avc_motion_estimation' extension instructions.
+
+; CHECK: OpCapability Groups
+; CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64"
+
+; CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+; CHECK-DAG: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+; CHECK-DAG: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+; CHECK-DAG: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+; CHECK-DAG: %[[#RefResultTy:]] = OpTypeAvcRefResultINTEL
+; CHECK-DAG: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+; CHECK-DAG: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+; CHECK-DAG: %[[#McePayloadTy:]] = OpTypeAvcMcePayloadINTEL
+; CHECK-DAG: %[[#MceResultTy:]] = OpTypeAvcMceResultINTEL
+
+; Function Attrs: convergent noinline nounwind optnone
+define spir_func void @test() #0 {
+entry:
+
+ %ime_payload = alloca target("spirv.AvcImePayloadINTEL"), align 8
+ %ime_result = alloca target("spirv.AvcImeResultINTEL"), align 8
+ %ref_payload = alloca target("spirv.AvcRefPayloadINTEL"), align 8
+ %ref_result = alloca target("spirv.AvcRefResultINTEL"), align 8
+ %sic_payload = alloca target("spirv.AvcSicPayloadINTEL"), align 8
+ %sic_result = alloca target("spirv.AvcSicResultINTEL"), align 8
+
+; CHECK: %[[#ImePayload:]] = OpLoad %[[#ImePayloadTy]]
+; CHECK: %[[#ImeResult:]] = OpLoad %[[#ImeResultTy]]
+; CHECK: %[[#RefPayload:]] = OpLoad %[[#RefPayloadTy]]
+; CHECK: %[[#RefResult:]] = OpLoad %[[#RefResultTy]]
+; CHECK: %[[#SicPayload:]] = OpLoad %[[#SicPayloadTy]]
+; CHECK: %[[#SicResult:]] = OpLoad %[[#SicResultTy]]
+
+ %0 = load target("spirv.AvcImePayloadINTEL"), target("spirv.AvcImePayloadINTEL")* %ime_payload, align 8
+ %1 = load target("spirv.AvcImeResultINTEL"), target("spirv.AvcImeResultINTEL")* %ime_result, align 8
+ %2 = load target("spirv.AvcRefPayloadINTEL"), target("spirv.AvcRefPayloadINTEL")* %ref_payload, align 8
+ %3 = load target("spirv.AvcRefResultINTEL"), target("spirv.AvcRefResultINTEL")* %ref_result, align 8
+ %4 = load target("spirv.AvcSicPayloadINTEL"), target("spirv.AvcSicPayloadINTEL")* %sic_payload, align 8
+ %5 = load target("spirv.AvcSicResultINTEL"), target("spirv.AvcSicResultINTEL")* %sic_result, align 8
+
+; CHECK: %[[#ImeMcePayloadConv:]] = OpSubgroupAvcImeConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#ImePayload]]
+; CHECK: %[[#McePayloadRet0:]] = OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#ImeMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToImePayloadINTEL
+; CHECK-SAME: %[[#ImePayloadTy]] %[[#McePayloadRet0]]
+ %call0 = call spir_func target("spirv.AvcImePayloadINTEL") @_Z62intel_sub_group_avc_ime_set_inter_base_multi_reference_penaltyh37ocl_intel_sub_group_avc_ime_payload_t(i8 zeroext 0, target("spirv.AvcImePayloadINTEL") %0) #2
+
+; CHECK: %[[#ImeMceResultConv:]] = OpSubgroupAvcImeConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#ImeResult]]
+; CHECK: OpSubgroupAvcMceGetMotionVectorsINTEL {{.*}} %[[#ImeMceResultConv]]
+ %call1 = call spir_func i64 @_Z42intel_sub_group_avc_ime_get_motion_vectors36ocl_intel_sub_group_avc_ime_result_t(target("spirv.AvcImeResultINTEL") %1) #2
+
+; CHECK: %[[#RefMcePayloadConv:]] = OpSubgroupAvcRefConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#RefPayload]]
+; CHECK: %[[#McePayloadRet1:]] = OpSubgroupAvcMceSetInterShapePenaltyINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#RefMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToRefPayloadINTEL
+; CHECK-SAME: %[[#RefPayloadTy]] %[[#McePayloadRet1]]
+ %call2 = call spir_func target("spirv.AvcRefPayloadINTEL") @_Z47intel_sub_group_avc_ref_set_inter_shape_penaltym37ocl_intel_sub_group_avc_ref_payload_t(i64 0, target("spirv.AvcRefPayloadINTEL") %2) #2
+
+; CHECK: %[[#RefMceResultConv:]] = OpSubgroupAvcRefConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#RefResult]]
+; CHECK: OpSubgroupAvcMceGetInterDistortionsINTEL {{.*}} %[[#RefMceResultConv]]
+ %call3 = call spir_func zeroext i16 @_Z45intel_sub_group_avc_ref_get_inter_distortions36ocl_intel_sub_group_avc_ref_result_t(target("spirv.AvcRefResultINTEL") %3) #2
+
+; CHECK: %[[#SicMcePayloadConv:]] = OpSubgroupAvcSicConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#SicPayload]]
+; CHECK: %[[#McePayloadRet2:]] = OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#SicMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToSicPayloadINTEL
+; CHECK-SAME: %[[#SicPayloadTy]] %[[#McePayloadRet2]]
+ %call4 = call spir_func target("spirv.AvcSicPayloadINTEL") @_Z55intel_sub_group_avc_sic_set_motion_vector_cost_functionmDv2_jh37ocl_intel_sub_group_avc_sic_payload_t(i64 0, <2 x i32> zeroinitializer, i8 zeroext 0, target("spirv.AvcSicPayloadINTEL") %4) #2
+
+; CHECK: %[[#SicMceResultConv:]] = OpSubgroupAvcSicConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#SicResult]]
+; CHECK: OpSubgroupAvcMceGetInterDistortionsINTEL {{.*}} %[[#SicMceResultConv]]
+ %call5 = call spir_func zeroext i16 @_Z45intel_sub_group_avc_sic_get_inter_distortions36ocl_intel_sub_group_avc_sic_result_t(target("spirv.AvcSicResultINTEL") %5) #2
+ ret void
+}
+
+; Function Attrs: convergent
+declare spir_func target("spirv.AvcImePayloadINTEL") @_Z62intel_sub_group_avc_ime_set_inter_base_multi_reference_penaltyh37ocl_intel_sub_group_avc_ime_payload_t(i8 zeroext, target("spirv.AvcImePayloadINTEL")) #1
+
+; Function Attrs: convergent
+declare spir_func i64 @_Z42intel_sub_group_avc_ime_get_motion_vectors36ocl_intel_sub_group_avc_ime_result_t(target("spirv.AvcImeResultINTEL")) #1
+
+; Function Attrs: convergent
+declare spir_func target("spirv.AvcRefPayloadINTEL") @_Z47intel_sub_group_avc_ref_set_inter_shape_penaltym37ocl_intel_sub_group_avc_ref_payload_t(i64, target("spirv.AvcRefPayloadINTEL")) #1
+
+; Function Attrs: convergent
+declare spir_func zeroext i16 @_Z45intel_sub_group_avc_ref_get_inter_distortions36ocl_intel_sub_group_avc_ref_result_t(target("spirv.AvcRefResultINTEL")) #1
+
+; Function Attrs: convergent
+declare spir_func target("spirv.AvcSicPayloadINTEL") @_Z55intel_sub_group_avc_sic_set_motion_vector_cost_functionmDv2_jh37ocl_intel_sub_group_avc_sic_payload_t(i64, <2 x i32>, i8 zeroext, target("spirv.AvcSicPayloadINTEL")) #1
+
+; Function Attrs: convergent
+declare spir_func zeroext i16 @_Z45intel_sub_group_avc_sic_get_inter_distortions36ocl_intel_sub_group_avc_sic_result_t(target("spirv.AvcSicResultINTEL")) #1
+
+attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { convergent "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { convergent }
+
+!llvm.module.flags = !{!0}
+!opencl.enable.FP_CONTRACT = !{}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!opencl.used.extensions = !{!2}
+!opencl.used.optional.core.features = !{!3}
+!opencl.compiler.options = !{!2}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 1, i32 2}
+!2 = !{}
+!3 = !{!"cl_images"}
+!4 = !{!"clang version 6.0.0"}
+
diff --git a/llvm/test/lit.cfg.py b/llvm/test/lit.cfg.py
index aad7a088551b2..2540eb83021f0 100644
--- a/llvm/test/lit.cfg.py
+++ b/llvm/test/lit.cfg.py
@@ -22,7 +22,7 @@
# suffixes: A list of file extensions to treat as test files. This is overriden
# by individual lit.local.cfg files in the test subdirectories.
-config.suffixes = [".ll", ".c", ".test", ".txt", ".s", ".mir", ".yaml", ".spv"]
+config.suffixes = [".ll", ".c", ".test", ".txt", ".s", ".mir", ".yaml", ".spv", ".cl"]
# excludes: A list of directories to exclude from the testsuite. The 'Inputs'
# subdirectories contain auxiliary inputs for various tests in their parent
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