[llvm] [RISCV] Add TuneNoDefaultUnroll to generic CPUs (PR #135318)

[Pengcheng Wang via llvm-commits]

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/135318

Almost all CPUs have added this.

We may enable it by default and remove this feature.

Fixes #134272.


>From af8e955ef862a3701f69b603e16bfead5c34d236 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 11 Apr 2025 11:51:50 +0800
Subject: [PATCH] [RISCV] Add TuneNoDefaultUnroll to generic CPUs

Almost all CPUs have added this.

We may enable it by default and remove this feature.

Fixes #134272.
---
 llvm/lib/Target/RISCV/RISCVProcessors.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 9d48adeec5e86..07a938db3e258 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -86,7 +86,8 @@ class RISCVTuneProcessorModel<string n,
                               list<SubtargetFeature> f = []>
     : ProcessorModel<n, m, f,tunef>;
 
-defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
+defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore,
+                              TuneNoDefaultUnroll];
 
 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
                                        NoSchedModel,