[llvm] [InstCombine] Combine and->cmp->sel->or-disjoint into and->mul (PR #135274)

[Yingwei Zheng via llvm-commits]

https://github.com/dtcxzyw requested changes to this pull request.

Do not use fixed-length integers.
Can you please provide a generalized alive2 proof?



https://github.com/llvm/llvm-project/pull/135274