[llvm] [AMDGPU][GlobalISel] Enable kernel argument preloading (PR #134655)

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<summary>
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.h
``````````

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<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
index d64884832..1e09d70c5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
@@ -517,28 +517,28 @@ void AMDGPUCallLowering::lowerPreloadedParameter(
   for (auto &&[Idx, PhysReg] : enumerate(PreloadRegs)) {
     Register VReg = MRI.getLiveInVirtReg(PhysReg);
     TypeSize RegSize = TRI->getRegSizeInBits(VReg, MRI);
-    
+
     if (!MRI.getVRegDef(VReg)) {
       MRI.setType(VReg, LLT::scalar(RegSize));
       B.getMBB().addLiveIn(PhysReg);
       B.buildInstr(TargetOpcode::COPY).addDef(VReg).addReg(PhysReg);
     }
-    
+
     if (DL.getTypeStoreSize(ArgTy) < 4 && Alignment < 4) {
       int64_t AlignDownOffset = alignDown(ArgOffset, 4);
       int64_t OffsetDiff = ArgOffset - AlignDownOffset;
       auto ShiftAmt = B.buildConstant(LLT::scalar(32), OffsetDiff * 8);
       auto Shift = B.buildRotateLeft(LLT::scalar(RegSize), VReg, ShiftAmt);
-      
+
       if (ResTy.isVector()) {
         B.buildBitcast(VRegs[0], B.buildTrunc(ScalarTy, Shift));
       } else {
         B.buildTrunc(VRegs[0], Shift);
       }
-      
+
       return;
     }
-    
+
     TotalSize += RegSize;
     SrcRegs[Idx] = VReg;
   }
@@ -573,9 +573,9 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
   CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
 
   allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
-  
+
   if (Subtarget->hasKernargPreload())
-  TLI.allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, MF, *TRI, *Info);
+    TLI.allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, MF, *TRI, *Info);
 
   unsigned i = 0;
   const Align KernArgBaseAlign(16);
@@ -626,7 +626,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
         Arg.hasInRegAttr() ? PreloadKernArgs.find(i) : PreloadKernArgs.end();
     if (PreloadKernArg != PreloadKernArgs.end()) {
       lowerPreloadedParameter(B, VRegs[i], ArgTy, ArgOffset, Alignment,
-                            PreloadKernArg->getSecond().Regs);
+                              PreloadKernArg->getSecond().Regs);
       ++i;
       continue;
     }
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
index 52663c748..74fce411e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h
@@ -31,8 +31,8 @@ class AMDGPUCallLowering final : public CallLowering {
                       Align Alignment) const;
 
   void lowerPreloadedParameter(MachineIRBuilder &B, ArrayRef<Register> VRegs,
-                             Type *ArgTy, uint64_t ArgOffset, Align Alignment,
-                             ArrayRef<MCRegister> PreloadRegs) const;
+                               Type *ArgTy, uint64_t ArgOffset, Align Alignment,
+                               ArrayRef<MCRegister> PreloadRegs) const;
 
   bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
                       SmallVectorImpl<BaseArgInfo> &Outs,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 8561aae98..653f18062 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1295,10 +1295,9 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
 
       unsigned PartOffset = 0;
       for (unsigned i = 0; i != NumRegs; ++i) {
-        State.addLoc(CCValAssign::getCustomMem(Arg.getArgNo(), RegisterVT,
-                                               BasePartOffset + PartOffset,
-                                               MemVT.getSimpleVT(),
-                                               CCValAssign::Full));
+        State.addLoc(CCValAssign::getCustomMem(
+            Arg.getArgNo(), RegisterVT, BasePartOffset + PartOffset,
+            MemVT.getSimpleVT(), CCValAssign::Full));
         PartOffset += MemVT.getStoreSize();
       }
     }
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index f9f1f9c95..15505f312 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2537,9 +2537,9 @@ void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
 }
 
 static bool allocPreloadKernArg(uint64_t &LastExplicitArgOffset,
-                                uint64_t ArgOffset,
-                                unsigned ArgSize, unsigned Idx,
-                                MachineFunction &MF, const SIRegisterInfo &TRI,
+                                uint64_t ArgOffset, unsigned ArgSize,
+                                unsigned Idx, MachineFunction &MF,
+                                const SIRegisterInfo &TRI,
                                 SIMachineFunctionInfo &Info, CCState &CCInfo) {
   GCNUserSGPRUsageInfo &SGPRInfo = Info.getUserSGPRInfo();
   const Align KernelArgBaseAlign = Align(16);

``````````

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https://github.com/llvm/llvm-project/pull/134655