[llvm] [SelectionDAG] Improve value type selection for inline asm within selected register class (PR #135097)

[Da Li 李达 via llvm-commits]

dlee992 wrote:

Unfortunately, my PR breaks dozens of lit tests across 5 targets:  
https://buildkite.com/llvm-project/github-pull-requests/builds/167049

I looked into one of the failures: `LLVM.CodeGen/RISCV/inline-asm-d-constraint-f.ll`, specifically the `constraint_gpr` function. My PR causes it to emit unnecessary `fmv` (bit-wise float-int move) instructions:

```asm
# %bb.0:
    fmv.d.x fa5, a0
    fmv.x.d a0, fa5
    #APP
    mv      a0, a0
    #NO_APP
    fmv.d.x fa5, a0
    fmv.x.d a0, fa5
    ret
```

This happens because of RISCV64's handling of `ZDINX` on RV64 — it **intentionally** allows `f64` in GPRs and uses the first value type in the `VTList` for the register class.

Other cases, like some in AMDGPU, require some instruction reordering. And there are even more issues I haven't fully investigated yet.

My current thinking: this original behavior has been around for a long time, and public target maintainers either:
- explicitly worked around it by tuning their `RegisterInfo` definitions and backend logic, or
- simply haven’t encountered it yet due to a lack of inline asm test coverage.

So, I think this work might need to be put on hold for now. What do you think? @arsenm . BTW, thanks for your valueable comments!


https://github.com/llvm/llvm-project/pull/135097