[llvm] c7745b0 - [AArch64][test] Regenerate arm64-st1.ll using update_llc_test_checks.py (NFC) (#134919)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 10 04:48:45 PDT 2025
Author: Benjamin Maxwell
Date: 2025-04-10T12:48:42+01:00
New Revision: c7745b0babb0151d9fe9cdc4fc180b0b53821e98
URL: https://github.com/llvm/llvm-project/commit/c7745b0babb0151d9fe9cdc4fc180b0b53821e98
DIFF: https://github.com/llvm/llvm-project/commit/c7745b0babb0151d9fe9cdc4fc180b0b53821e98.diff
LOG: [AArch64][test] Regenerate arm64-st1.ll using update_llc_test_checks.py (NFC) (#134919)
This is a fairly large test file which can be annoying to manually
update. Using --filter-out gets pretty close to the original checks.
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-st1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-st1.ll b/llvm/test/CodeGen/AArch64/arm64-st1.ll
index 6f87c66c87345..02797f3ed186c 100644
--- a/llvm/test/CodeGen/AArch64/arm64-st1.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-st1.ll
@@ -1,11 +1,14 @@
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "(kill|%bb|ret)" --version 5
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,SD-CHECK
+; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,GI-CHECK
; The instruction latencies of Exynos-M3 trigger the transform we see under the Exynos check.
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m3 | FileCheck --check-prefix=EXYNOS %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m3 | FileCheck --check-prefixes=CHECK,EXYNOS %s
define void @st1lane_16b(<16 x i8> %A, ptr %D) {
-; CHECK-LABEL: st1lane_16b
-; CHECK: st1.b { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_16b:
+; CHECK: add x8, x0, #1
+; CHECK: st1.b { v0 }[1], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 1
%tmp = extractelement <16 x i8> %A, i32 1
store i8 %tmp, ptr %ptr
@@ -13,8 +16,10 @@ define void @st1lane_16b(<16 x i8> %A, ptr %D) {
}
define void @st1lane0_16b(<16 x i8> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_16b
-; CHECK: st1.b { v0 }[0], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane0_16b:
+; CHECK: add x8, x0, #1
+; CHECK: st1.b { v0 }[0], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 1
%tmp = extractelement <16 x i8> %A, i32 0
store i8 %tmp, ptr %ptr
@@ -22,8 +27,10 @@ define void @st1lane0_16b(<16 x i8> %A, ptr %D) {
}
define void @st1lane0u_16b(<16 x i8> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_16b
-; CHECK: st1.b { v0 }[0], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane0u_16b:
+; CHECK: sub x8, x0, #1
+; CHECK: st1.b { v0 }[0], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 -1
%tmp = extractelement <16 x i8> %A, i32 0
store i8 %tmp, ptr %ptr
@@ -31,9 +38,10 @@ define void @st1lane0u_16b(<16 x i8> %A, ptr %D) {
}
define void @st1lane_ro_16b(<16 x i8> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_16b
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.b { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_16b:
+; CHECK: add x8, x0, x1
+; CHECK: st1.b { v0 }[1], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 %offset
%tmp = extractelement <16 x i8> %A, i32 1
store i8 %tmp, ptr %ptr
@@ -41,9 +49,10 @@ define void @st1lane_ro_16b(<16 x i8> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_16b(<16 x i8> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_16b
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.b { v0 }[0], [x[[XREG]]]
+; CHECK-LABEL: st1lane0_ro_16b:
+; CHECK: add x8, x0, x1
+; CHECK: st1.b { v0 }[0], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 %offset
%tmp = extractelement <16 x i8> %A, i32 0
store i8 %tmp, ptr %ptr
@@ -51,8 +60,9 @@ define void @st1lane0_ro_16b(<16 x i8> %A, ptr %D, i64 %offset) {
}
define void @st1lane_8h(<8 x i16> %A, ptr %D) {
-; CHECK-LABEL: st1lane_8h
-; CHECK: st1.h { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_8h:
+; CHECK: add x8, x0, #2
+; CHECK: st1.h { v0 }[1], [x8]
%ptr = getelementptr i16, ptr %D, i64 1
%tmp = extractelement <8 x i16> %A, i32 1
store i16 %tmp, ptr %ptr
@@ -60,8 +70,8 @@ define void @st1lane_8h(<8 x i16> %A, ptr %D) {
}
define void @st1lane0_8h(<8 x i16> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_8h
-; CHECK: str h0, [x0, #2]
+; CHECK-LABEL: st1lane0_8h:
+; CHECK: str h0, [x0, #2]
%ptr = getelementptr i16, ptr %D, i64 1
%tmp = extractelement <8 x i16> %A, i32 0
store i16 %tmp, ptr %ptr
@@ -69,8 +79,8 @@ define void @st1lane0_8h(<8 x i16> %A, ptr %D) {
}
define void @st1lane0u_8h(<8 x i16> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_8h
-; CHECK: stur h0, [x0, #-2]
+; CHECK-LABEL: st1lane0u_8h:
+; CHECK: stur h0, [x0, #-2]
%ptr = getelementptr i16, ptr %D, i64 -1
%tmp = extractelement <8 x i16> %A, i32 0
store i16 %tmp, ptr %ptr
@@ -78,9 +88,9 @@ define void @st1lane0u_8h(<8 x i16> %A, ptr %D) {
}
define void @st1lane_ro_8h(<8 x i16> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_8h
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.h { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_8h:
+; CHECK: add x8, x0, x1, lsl #1
+; CHECK: st1.h { v0 }[1], [x8]
%ptr = getelementptr i16, ptr %D, i64 %offset
%tmp = extractelement <8 x i16> %A, i32 1
store i16 %tmp, ptr %ptr
@@ -88,8 +98,8 @@ define void @st1lane_ro_8h(<8 x i16> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_8h(<8 x i16> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_8h
-; CHECK: str h0, [x0, x1, lsl #1]
+; CHECK-LABEL: st1lane0_ro_8h:
+; CHECK: str h0, [x0, x1, lsl #1]
%ptr = getelementptr i16, ptr %D, i64 %offset
%tmp = extractelement <8 x i16> %A, i32 0
store i16 %tmp, ptr %ptr
@@ -97,8 +107,9 @@ define void @st1lane0_ro_8h(<8 x i16> %A, ptr %D, i64 %offset) {
}
define void @st1lane_4s(<4 x i32> %A, ptr %D) {
-; CHECK-LABEL: st1lane_4s
-; CHECK: st1.s { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_4s:
+; CHECK: add x8, x0, #4
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr i32, ptr %D, i64 1
%tmp = extractelement <4 x i32> %A, i32 1
store i32 %tmp, ptr %ptr
@@ -106,8 +117,8 @@ define void @st1lane_4s(<4 x i32> %A, ptr %D) {
}
define void @st1lane0_4s(<4 x i32> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_4s
-; CHECK: str s0, [x0, #4]
+; CHECK-LABEL: st1lane0_4s:
+; CHECK: str s0, [x0, #4]
%ptr = getelementptr i32, ptr %D, i64 1
%tmp = extractelement <4 x i32> %A, i32 0
store i32 %tmp, ptr %ptr
@@ -115,8 +126,8 @@ define void @st1lane0_4s(<4 x i32> %A, ptr %D) {
}
define void @st1lane0u_4s(<4 x i32> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_4s
-; CHECK: stur s0, [x0, #-4]
+; CHECK-LABEL: st1lane0u_4s:
+; CHECK: stur s0, [x0, #-4]
%ptr = getelementptr i32, ptr %D, i64 -1
%tmp = extractelement <4 x i32> %A, i32 0
store i32 %tmp, ptr %ptr
@@ -124,9 +135,9 @@ define void @st1lane0u_4s(<4 x i32> %A, ptr %D) {
}
define void @st1lane_ro_4s(<4 x i32> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_4s
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.s { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_4s:
+; CHECK: add x8, x0, x1, lsl #2
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr i32, ptr %D, i64 %offset
%tmp = extractelement <4 x i32> %A, i32 1
store i32 %tmp, ptr %ptr
@@ -134,8 +145,8 @@ define void @st1lane_ro_4s(<4 x i32> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_4s(<4 x i32> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_4s
-; CHECK: str s0, [x0, x1, lsl #2]
+; CHECK-LABEL: st1lane0_ro_4s:
+; CHECK: str s0, [x0, x1, lsl #2]
%ptr = getelementptr i32, ptr %D, i64 %offset
%tmp = extractelement <4 x i32> %A, i32 0
store i32 %tmp, ptr %ptr
@@ -143,8 +154,9 @@ define void @st1lane0_ro_4s(<4 x i32> %A, ptr %D, i64 %offset) {
}
define void @st1lane_4s_float(<4 x float> %A, ptr %D) {
-; CHECK-LABEL: st1lane_4s_float
-; CHECK: st1.s { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_4s_float:
+; CHECK: add x8, x0, #4
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr float, ptr %D, i64 1
%tmp = extractelement <4 x float> %A, i32 1
store float %tmp, ptr %ptr
@@ -152,8 +164,8 @@ define void @st1lane_4s_float(<4 x float> %A, ptr %D) {
}
define void @st1lane0_4s_float(<4 x float> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_4s_float
-; CHECK: str s0, [x0, #4]
+; CHECK-LABEL: st1lane0_4s_float:
+; CHECK: str s0, [x0, #4]
%ptr = getelementptr float, ptr %D, i64 1
%tmp = extractelement <4 x float> %A, i32 0
store float %tmp, ptr %ptr
@@ -161,8 +173,8 @@ define void @st1lane0_4s_float(<4 x float> %A, ptr %D) {
}
define void @st1lane0u_4s_float(<4 x float> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_4s_float
-; CHECK: stur s0, [x0, #-4]
+; CHECK-LABEL: st1lane0u_4s_float:
+; CHECK: stur s0, [x0, #-4]
%ptr = getelementptr float, ptr %D, i64 -1
%tmp = extractelement <4 x float> %A, i32 0
store float %tmp, ptr %ptr
@@ -170,9 +182,9 @@ define void @st1lane0u_4s_float(<4 x float> %A, ptr %D) {
}
define void @st1lane_ro_4s_float(<4 x float> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_4s_float
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.s { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_4s_float:
+; CHECK: add x8, x0, x1, lsl #2
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr float, ptr %D, i64 %offset
%tmp = extractelement <4 x float> %A, i32 1
store float %tmp, ptr %ptr
@@ -180,8 +192,8 @@ define void @st1lane_ro_4s_float(<4 x float> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_4s_float(<4 x float> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_4s_float
-; CHECK: str s0, [x0, x1, lsl #2]
+; CHECK-LABEL: st1lane0_ro_4s_float:
+; CHECK: str s0, [x0, x1, lsl #2]
%ptr = getelementptr float, ptr %D, i64 %offset
%tmp = extractelement <4 x float> %A, i32 0
store float %tmp, ptr %ptr
@@ -189,8 +201,9 @@ define void @st1lane0_ro_4s_float(<4 x float> %A, ptr %D, i64 %offset) {
}
define void @st1lane_2d(<2 x i64> %A, ptr %D) {
-; CHECK-LABEL: st1lane_2d
-; CHECK: st1.d { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_2d:
+; CHECK: add x8, x0, #8
+; CHECK: st1.d { v0 }[1], [x8]
%ptr = getelementptr i64, ptr %D, i64 1
%tmp = extractelement <2 x i64> %A, i32 1
store i64 %tmp, ptr %ptr
@@ -198,8 +211,8 @@ define void @st1lane_2d(<2 x i64> %A, ptr %D) {
}
define void @st1lane0_2d(<2 x i64> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_2d
-; CHECK: str d0, [x0, #8]
+; CHECK-LABEL: st1lane0_2d:
+; CHECK: str d0, [x0, #8]
%ptr = getelementptr i64, ptr %D, i64 1
%tmp = extractelement <2 x i64> %A, i32 0
store i64 %tmp, ptr %ptr
@@ -207,8 +220,8 @@ define void @st1lane0_2d(<2 x i64> %A, ptr %D) {
}
define void @st1lane0u_2d(<2 x i64> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_2d
-; CHECK: stur d0, [x0, #-8]
+; CHECK-LABEL: st1lane0u_2d:
+; CHECK: stur d0, [x0, #-8]
%ptr = getelementptr i64, ptr %D, i64 -1
%tmp = extractelement <2 x i64> %A, i32 0
store i64 %tmp, ptr %ptr
@@ -216,9 +229,9 @@ define void @st1lane0u_2d(<2 x i64> %A, ptr %D) {
}
define void @st1lane_ro_2d(<2 x i64> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_2d
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.d { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_2d:
+; CHECK: add x8, x0, x1, lsl #3
+; CHECK: st1.d { v0 }[1], [x8]
%ptr = getelementptr i64, ptr %D, i64 %offset
%tmp = extractelement <2 x i64> %A, i32 1
store i64 %tmp, ptr %ptr
@@ -226,8 +239,8 @@ define void @st1lane_ro_2d(<2 x i64> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_2d(<2 x i64> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_2d
-; CHECK: str d0, [x0, x1, lsl #3]
+; CHECK-LABEL: st1lane0_ro_2d:
+; CHECK: str d0, [x0, x1, lsl #3]
%ptr = getelementptr i64, ptr %D, i64 %offset
%tmp = extractelement <2 x i64> %A, i32 0
store i64 %tmp, ptr %ptr
@@ -235,8 +248,9 @@ define void @st1lane0_ro_2d(<2 x i64> %A, ptr %D, i64 %offset) {
}
define void @st1lane_2d_double(<2 x double> %A, ptr %D) {
-; CHECK-LABEL: st1lane_2d_double
-; CHECK: st1.d { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_2d_double:
+; CHECK: add x8, x0, #8
+; CHECK: st1.d { v0 }[1], [x8]
%ptr = getelementptr double, ptr %D, i64 1
%tmp = extractelement <2 x double> %A, i32 1
store double %tmp, ptr %ptr
@@ -244,8 +258,8 @@ define void @st1lane_2d_double(<2 x double> %A, ptr %D) {
}
define void @st1lane0_2d_double(<2 x double> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_2d_double
-; CHECK: str d0, [x0, #8]
+; CHECK-LABEL: st1lane0_2d_double:
+; CHECK: str d0, [x0, #8]
%ptr = getelementptr double, ptr %D, i64 1
%tmp = extractelement <2 x double> %A, i32 0
store double %tmp, ptr %ptr
@@ -253,8 +267,8 @@ define void @st1lane0_2d_double(<2 x double> %A, ptr %D) {
}
define void @st1lane0u_2d_double(<2 x double> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_2d_double
-; CHECK: stur d0, [x0, #-8]
+; CHECK-LABEL: st1lane0u_2d_double:
+; CHECK: stur d0, [x0, #-8]
%ptr = getelementptr double, ptr %D, i64 -1
%tmp = extractelement <2 x double> %A, i32 0
store double %tmp, ptr %ptr
@@ -262,9 +276,9 @@ define void @st1lane0u_2d_double(<2 x double> %A, ptr %D) {
}
define void @st1lane_ro_2d_double(<2 x double> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_2d_double
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.d { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_2d_double:
+; CHECK: add x8, x0, x1, lsl #3
+; CHECK: st1.d { v0 }[1], [x8]
%ptr = getelementptr double, ptr %D, i64 %offset
%tmp = extractelement <2 x double> %A, i32 1
store double %tmp, ptr %ptr
@@ -272,8 +286,8 @@ define void @st1lane_ro_2d_double(<2 x double> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_2d_double(<2 x double> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_2d_double
-; CHECK: str d0, [x0, x1, lsl #3]
+; CHECK-LABEL: st1lane0_ro_2d_double:
+; CHECK: str d0, [x0, x1, lsl #3]
%ptr = getelementptr double, ptr %D, i64 %offset
%tmp = extractelement <2 x double> %A, i32 0
store double %tmp, ptr %ptr
@@ -281,8 +295,10 @@ define void @st1lane0_ro_2d_double(<2 x double> %A, ptr %D, i64 %offset) {
}
define void @st1lane_8b(<8 x i8> %A, ptr %D) {
-; CHECK-LABEL: st1lane_8b
-; CHECK: st1.b { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_8b:
+; CHECK: add x8, x0, #1
+; CHECK: st1.b { v0 }[1], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 1
%tmp = extractelement <8 x i8> %A, i32 1
store i8 %tmp, ptr %ptr
@@ -290,9 +306,10 @@ define void @st1lane_8b(<8 x i8> %A, ptr %D) {
}
define void @st1lane_ro_8b(<8 x i8> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_8b
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.b { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_8b:
+; CHECK: add x8, x0, x1
+; CHECK: st1.b { v0 }[1], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 %offset
%tmp = extractelement <8 x i8> %A, i32 1
store i8 %tmp, ptr %ptr
@@ -300,9 +317,10 @@ define void @st1lane_ro_8b(<8 x i8> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_8b(<8 x i8> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_8b
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.b { v0 }[0], [x[[XREG]]]
+; CHECK-LABEL: st1lane0_ro_8b:
+; CHECK: add x8, x0, x1
+; CHECK: st1.b { v0 }[0], [x8]
+
%ptr = getelementptr i8, ptr %D, i64 %offset
%tmp = extractelement <8 x i8> %A, i32 0
store i8 %tmp, ptr %ptr
@@ -310,8 +328,9 @@ define void @st1lane0_ro_8b(<8 x i8> %A, ptr %D, i64 %offset) {
}
define void @st1lane_4h(<4 x i16> %A, ptr %D) {
-; CHECK-LABEL: st1lane_4h
-; CHECK: st1.h { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_4h:
+; CHECK: add x8, x0, #2
+; CHECK: st1.h { v0 }[1], [x8]
%ptr = getelementptr i16, ptr %D, i64 1
%tmp = extractelement <4 x i16> %A, i32 1
store i16 %tmp, ptr %ptr
@@ -319,8 +338,8 @@ define void @st1lane_4h(<4 x i16> %A, ptr %D) {
}
define void @st1lane0_4h(<4 x i16> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_4h
-; CHECK: str h0, [x0, #2]
+; CHECK-LABEL: st1lane0_4h:
+; CHECK: str h0, [x0, #2]
%ptr = getelementptr i16, ptr %D, i64 1
%tmp = extractelement <4 x i16> %A, i32 0
store i16 %tmp, ptr %ptr
@@ -328,8 +347,8 @@ define void @st1lane0_4h(<4 x i16> %A, ptr %D) {
}
define void @st1lane0u_4h(<4 x i16> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_4h
-; CHECK: stur h0, [x0, #-2]
+; CHECK-LABEL: st1lane0u_4h:
+; CHECK: stur h0, [x0, #-2]
%ptr = getelementptr i16, ptr %D, i64 -1
%tmp = extractelement <4 x i16> %A, i32 0
store i16 %tmp, ptr %ptr
@@ -337,9 +356,9 @@ define void @st1lane0u_4h(<4 x i16> %A, ptr %D) {
}
define void @st1lane_ro_4h(<4 x i16> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_4h
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.h { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_4h:
+; CHECK: add x8, x0, x1, lsl #1
+; CHECK: st1.h { v0 }[1], [x8]
%ptr = getelementptr i16, ptr %D, i64 %offset
%tmp = extractelement <4 x i16> %A, i32 1
store i16 %tmp, ptr %ptr
@@ -347,8 +366,8 @@ define void @st1lane_ro_4h(<4 x i16> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_4h(<4 x i16> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_4h
-; CHECK: str h0, [x0, x1, lsl #1]
+; CHECK-LABEL: st1lane0_ro_4h:
+; CHECK: str h0, [x0, x1, lsl #1]
%ptr = getelementptr i16, ptr %D, i64 %offset
%tmp = extractelement <4 x i16> %A, i32 0
store i16 %tmp, ptr %ptr
@@ -356,8 +375,9 @@ define void @st1lane0_ro_4h(<4 x i16> %A, ptr %D, i64 %offset) {
}
define void @st1lane_2s(<2 x i32> %A, ptr %D) {
-; CHECK-LABEL: st1lane_2s
-; CHECK: st1.s { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_2s:
+; CHECK: add x8, x0, #4
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr i32, ptr %D, i64 1
%tmp = extractelement <2 x i32> %A, i32 1
store i32 %tmp, ptr %ptr
@@ -365,8 +385,8 @@ define void @st1lane_2s(<2 x i32> %A, ptr %D) {
}
define void @st1lane0_2s(<2 x i32> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_2s
-; CHECK: str s0, [x0, #4]
+; CHECK-LABEL: st1lane0_2s:
+; CHECK: str s0, [x0, #4]
%ptr = getelementptr i32, ptr %D, i64 1
%tmp = extractelement <2 x i32> %A, i32 0
store i32 %tmp, ptr %ptr
@@ -374,8 +394,8 @@ define void @st1lane0_2s(<2 x i32> %A, ptr %D) {
}
define void @st1lane0u_2s(<2 x i32> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_2s
-; CHECK: stur s0, [x0, #-4]
+; CHECK-LABEL: st1lane0u_2s:
+; CHECK: stur s0, [x0, #-4]
%ptr = getelementptr i32, ptr %D, i64 -1
%tmp = extractelement <2 x i32> %A, i32 0
store i32 %tmp, ptr %ptr
@@ -383,9 +403,9 @@ define void @st1lane0u_2s(<2 x i32> %A, ptr %D) {
}
define void @st1lane_ro_2s(<2 x i32> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_2s
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.s { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_2s:
+; CHECK: add x8, x0, x1, lsl #2
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr i32, ptr %D, i64 %offset
%tmp = extractelement <2 x i32> %A, i32 1
store i32 %tmp, ptr %ptr
@@ -393,8 +413,8 @@ define void @st1lane_ro_2s(<2 x i32> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_2s(<2 x i32> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_2s
-; CHECK: str s0, [x0, x1, lsl #2]
+; CHECK-LABEL: st1lane0_ro_2s:
+; CHECK: str s0, [x0, x1, lsl #2]
%ptr = getelementptr i32, ptr %D, i64 %offset
%tmp = extractelement <2 x i32> %A, i32 0
store i32 %tmp, ptr %ptr
@@ -402,8 +422,9 @@ define void @st1lane0_ro_2s(<2 x i32> %A, ptr %D, i64 %offset) {
}
define void @st1lane_2s_float(<2 x float> %A, ptr %D) {
-; CHECK-LABEL: st1lane_2s_float
-; CHECK: st1.s { v0 }[1], [x{{[0-9]+}}]
+; CHECK-LABEL: st1lane_2s_float:
+; CHECK: add x8, x0, #4
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr float, ptr %D, i64 1
%tmp = extractelement <2 x float> %A, i32 1
store float %tmp, ptr %ptr
@@ -411,8 +432,8 @@ define void @st1lane_2s_float(<2 x float> %A, ptr %D) {
}
define void @st1lane0_2s_float(<2 x float> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_2s_float
-; CHECK: str s0, [x0, #4]
+; CHECK-LABEL: st1lane0_2s_float:
+; CHECK: str s0, [x0, #4]
%ptr = getelementptr float, ptr %D, i64 1
%tmp = extractelement <2 x float> %A, i32 0
store float %tmp, ptr %ptr
@@ -420,8 +441,8 @@ define void @st1lane0_2s_float(<2 x float> %A, ptr %D) {
}
define void @st1lane0u_2s_float(<2 x float> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_2s_float
-; CHECK: stur s0, [x0, #-4]
+; CHECK-LABEL: st1lane0u_2s_float:
+; CHECK: stur s0, [x0, #-4]
%ptr = getelementptr float, ptr %D, i64 -1
%tmp = extractelement <2 x float> %A, i32 0
store float %tmp, ptr %ptr
@@ -429,9 +450,9 @@ define void @st1lane0u_2s_float(<2 x float> %A, ptr %D) {
}
define void @st1lane_ro_2s_float(<2 x float> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane_ro_2s_float
-; CHECK: add x[[XREG:[0-9]+]], x0, x1
-; CHECK: st1.s { v0 }[1], [x[[XREG]]]
+; CHECK-LABEL: st1lane_ro_2s_float:
+; CHECK: add x8, x0, x1, lsl #2
+; CHECK: st1.s { v0 }[1], [x8]
%ptr = getelementptr float, ptr %D, i64 %offset
%tmp = extractelement <2 x float> %A, i32 1
store float %tmp, ptr %ptr
@@ -439,8 +460,8 @@ define void @st1lane_ro_2s_float(<2 x float> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_ro_2s_float(<2 x float> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_2s_float
-; CHECK: str s0, [x0, x1, lsl #2]
+; CHECK-LABEL: st1lane0_ro_2s_float:
+; CHECK: str s0, [x0, x1, lsl #2]
%ptr = getelementptr float, ptr %D, i64 %offset
%tmp = extractelement <2 x float> %A, i32 0
store float %tmp, ptr %ptr
@@ -448,8 +469,8 @@ define void @st1lane0_ro_2s_float(<2 x float> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_1d(<1 x i64> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_1d
-; CHECK: str d0, [x0, #8]
+; CHECK-LABEL: st1lane0_1d:
+; CHECK: str d0, [x0, #8]
%ptr = getelementptr i64, ptr %D, i64 1
%tmp = extractelement <1 x i64> %A, i32 0
store i64 %tmp, ptr %ptr
@@ -457,8 +478,8 @@ define void @st1lane0_1d(<1 x i64> %A, ptr %D) {
}
define void @st1lane0u_1d(<1 x i64> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_1d
-; CHECK: stur d0, [x0, #-8]
+; CHECK-LABEL: st1lane0u_1d:
+; CHECK: stur d0, [x0, #-8]
%ptr = getelementptr i64, ptr %D, i64 -1
%tmp = extractelement <1 x i64> %A, i32 0
store i64 %tmp, ptr %ptr
@@ -466,8 +487,8 @@ define void @st1lane0u_1d(<1 x i64> %A, ptr %D) {
}
define void @st1lane0_ro_1d(<1 x i64> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_1d
-; CHECK: str d0, [x0, x1, lsl #3]
+; CHECK-LABEL: st1lane0_ro_1d:
+; CHECK: str d0, [x0, x1, lsl #3]
%ptr = getelementptr i64, ptr %D, i64 %offset
%tmp = extractelement <1 x i64> %A, i32 0
store i64 %tmp, ptr %ptr
@@ -475,8 +496,8 @@ define void @st1lane0_ro_1d(<1 x i64> %A, ptr %D, i64 %offset) {
}
define void @st1lane0_1d_double(<1 x double> %A, ptr %D) {
-; CHECK-LABEL: st1lane0_1d_double
-; CHECK: str d0, [x0, #8]
+; CHECK-LABEL: st1lane0_1d_double:
+; CHECK: str d0, [x0, #8]
%ptr = getelementptr double, ptr %D, i64 1
%tmp = extractelement <1 x double> %A, i32 0
store double %tmp, ptr %ptr
@@ -484,8 +505,8 @@ define void @st1lane0_1d_double(<1 x double> %A, ptr %D) {
}
define void @st1lane0u_1d_double(<1 x double> %A, ptr %D) {
-; CHECK-LABEL: st1lane0u_1d_double
-; CHECK: stur d0, [x0, #-8]
+; CHECK-LABEL: st1lane0u_1d_double:
+; CHECK: stur d0, [x0, #-8]
%ptr = getelementptr double, ptr %D, i64 -1
%tmp = extractelement <1 x double> %A, i32 0
store double %tmp, ptr %ptr
@@ -493,8 +514,8 @@ define void @st1lane0u_1d_double(<1 x double> %A, ptr %D) {
}
define void @st1lane0_ro_1d_double(<1 x double> %A, ptr %D, i64 %offset) {
-; CHECK-LABEL: st1lane0_ro_1d_double
-; CHECK: str d0, [x0, x1, lsl #3]
+; CHECK-LABEL: st1lane0_ro_1d_double:
+; CHECK: str d0, [x0, x1, lsl #3]
%ptr = getelementptr double, ptr %D, i64 %offset
%tmp = extractelement <1 x double> %A, i32 0
store double %tmp, ptr %ptr
@@ -502,29 +523,29 @@ define void @st1lane0_ro_1d_double(<1 x double> %A, ptr %D, i64 %offset) {
}
define void @st2lane_16b(<16 x i8> %A, <16 x i8> %B, ptr %D) {
-; CHECK-LABEL: st2lane_16b
-; CHECK: st2.b
+; CHECK-LABEL: st2lane_16b:
+; CHECK: st2.b { v0, v1 }[1], [x0]
call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> %A, <16 x i8> %B, i64 1, ptr %D)
ret void
}
define void @st2lane_8h(<8 x i16> %A, <8 x i16> %B, ptr %D) {
-; CHECK-LABEL: st2lane_8h
-; CHECK: st2.h
+; CHECK-LABEL: st2lane_8h:
+; CHECK: st2.h { v0, v1 }[1], [x0]
call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> %A, <8 x i16> %B, i64 1, ptr %D)
ret void
}
define void @st2lane_4s(<4 x i32> %A, <4 x i32> %B, ptr %D) {
-; CHECK-LABEL: st2lane_4s
-; CHECK: st2.s
+; CHECK-LABEL: st2lane_4s:
+; CHECK: st2.s { v0, v1 }[1], [x0]
call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> %A, <4 x i32> %B, i64 1, ptr %D)
ret void
}
define void @st2lane_2d(<2 x i64> %A, <2 x i64> %B, ptr %D) {
-; CHECK-LABEL: st2lane_2d
-; CHECK: st2.d
+; CHECK-LABEL: st2lane_2d:
+; CHECK: st2.d { v0, v1 }[1], [x0]
call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> %A, <2 x i64> %B, i64 1, ptr %D)
ret void
}
@@ -535,29 +556,29 @@ declare void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32>, <4 x i32>, i64, ptr)
declare void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64>, <2 x i64>, i64, ptr) nounwind readnone
define void @st3lane_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %D) {
-; CHECK-LABEL: st3lane_16b
-; CHECK: st3.b
+; CHECK-LABEL: st3lane_16b:
+; CHECK: st3.b { v0, v1, v2 }[1], [x0]
call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i64 1, ptr %D)
ret void
}
define void @st3lane_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %D) {
-; CHECK-LABEL: st3lane_8h
-; CHECK: st3.h
+; CHECK-LABEL: st3lane_8h:
+; CHECK: st3.h { v0, v1, v2 }[1], [x0]
call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i64 1, ptr %D)
ret void
}
define void @st3lane_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %D) {
-; CHECK-LABEL: st3lane_4s
-; CHECK: st3.s
+; CHECK-LABEL: st3lane_4s:
+; CHECK: st3.s { v0, v1, v2 }[1], [x0]
call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i64 1, ptr %D)
ret void
}
define void @st3lane_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %D) {
-; CHECK-LABEL: st3lane_2d
-; CHECK: st3.d
+; CHECK-LABEL: st3lane_2d:
+; CHECK: st3.d { v0, v1, v2 }[1], [x0]
call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64 1, ptr %D)
ret void
}
@@ -568,29 +589,29 @@ declare void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>
declare void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, i64, ptr) nounwind readnone
define void @st4lane_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %E) {
-; CHECK-LABEL: st4lane_16b
-; CHECK: st4.b
+; CHECK-LABEL: st4lane_16b:
+; CHECK: st4.b { v0, v1, v2, v3 }[1], [x0]
call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 1, ptr %E)
ret void
}
define void @st4lane_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %E) {
-; CHECK-LABEL: st4lane_8h
-; CHECK: st4.h
+; CHECK-LABEL: st4lane_8h:
+; CHECK: st4.h { v0, v1, v2, v3 }[1], [x0]
call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 1, ptr %E)
ret void
}
define void @st4lane_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %E) {
-; CHECK-LABEL: st4lane_4s
-; CHECK: st4.s
+; CHECK-LABEL: st4lane_4s:
+; CHECK: st4.s { v0, v1, v2, v3 }[1], [x0]
call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 1, ptr %E)
ret void
}
define void @st4lane_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %E) {
-; CHECK-LABEL: st4lane_2d
-; CHECK: st4.d
+; CHECK-LABEL: st4lane_2d:
+; CHECK: st4.d { v0, v1, v2, v3 }[1], [x0]
call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 1, ptr %E)
ret void
}
@@ -602,37 +623,45 @@ declare void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>
define void @st2_8b(<8 x i8> %A, <8 x i8> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_8b
-; CHECK: st2.8b
-; EXYNOS-LABEL: st2_8b
-; EXYNOS: zip1.8b
-; EXYNOS: zip2.8b
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_8b:
+; SD-CHECK: st2.8b { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_8b:
+; GI-CHECK: st2.8b { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_8b:
+; EXYNOS: zip1.8b v2, v0, v1
+; EXYNOS: zip2.8b v0, v0, v1
+; EXYNOS: stp d2, d0, [x0]
call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %A, <8 x i8> %B, ptr %P)
ret void
}
define void @st3_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_8b
-; CHECK: st3.8b
+; CHECK-LABEL: st3_8b:
+; CHECK: st3.8b { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %P)
ret void
}
define void @st4_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_8b
-; CHECK: st4.8b
-; EXYNOS-LABEL: st4_8b
-; EXYNOS: zip1.8b
-; EXYNOS: zip2.8b
-; EXYNOS: zip1.8b
-; EXYNOS: zip2.8b
-; EXYNOS: zip1.8b
-; EXYNOS: zip2.8b
-; EXYNOS: stp
-; EXYNOS: zip1.8b
-; EXYNOS: zip2.8b
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_8b:
+; SD-CHECK: st4.8b { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_8b:
+; GI-CHECK: st4.8b { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_8b:
+; EXYNOS: zip1.8b v4, v0, v2
+; EXYNOS: zip2.8b v0, v0, v2
+; EXYNOS: zip1.8b v2, v1, v3
+; EXYNOS: zip2.8b v1, v1, v3
+; EXYNOS: zip1.8b v3, v4, v2
+; EXYNOS: zip2.8b v2, v4, v2
+; EXYNOS: stp d3, d2, [x0]
+; EXYNOS: zip1.8b v4, v0, v1
+; EXYNOS: zip2.8b v0, v0, v1
+; EXYNOS: stp d4, d0, [x0, #16]
call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %P)
ret void
}
@@ -642,37 +671,45 @@ declare void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, ptr) n
declare void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, ptr) nounwind readonly
define void @st2_16b(<16 x i8> %A, <16 x i8> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_16b
-; CHECK: st2.16b
-; EXYNOS-LABEL: st2_16b
-; EXYNOS: zip1.16b
-; EXYNOS: zip2.16b
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_16b:
+; SD-CHECK: st2.16b { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_16b:
+; GI-CHECK: st2.16b { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_16b:
+; EXYNOS: zip1.16b v2, v0, v1
+; EXYNOS: zip2.16b v0, v0, v1
+; EXYNOS: stp q2, q0, [x0]
call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> %A, <16 x i8> %B, ptr %P)
ret void
}
define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_16b
-; CHECK: st3.16b
+; CHECK-LABEL: st3_16b:
+; CHECK: st3.16b { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %P)
ret void
}
define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_16b
-; CHECK: st4.16b
-; EXYNOS-LABEL: st4_16b
-; EXYNOS: zip1.16b
-; EXYNOS: zip2.16b
-; EXYNOS: zip1.16b
-; EXYNOS: zip2.16b
-; EXYNOS: zip1.16b
-; EXYNOS: zip2.16b
-; EXYNOS: stp
-; EXYNOS: zip1.16b
-; EXYNOS: zip2.16b
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_16b:
+; SD-CHECK: st4.16b { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_16b:
+; GI-CHECK: st4.16b { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_16b:
+; EXYNOS: zip1.16b v4, v0, v2
+; EXYNOS: zip2.16b v0, v0, v2
+; EXYNOS: zip1.16b v2, v1, v3
+; EXYNOS: zip2.16b v1, v1, v3
+; EXYNOS: zip1.16b v3, v4, v2
+; EXYNOS: zip2.16b v2, v4, v2
+; EXYNOS: stp q3, q2, [x0]
+; EXYNOS: zip1.16b v4, v0, v1
+; EXYNOS: zip2.16b v0, v0, v1
+; EXYNOS: stp q4, q0, [x0, #32]
call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %P)
ret void
}
@@ -682,37 +719,45 @@ declare void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, pt
declare void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind readonly
define void @st2_4h(<4 x i16> %A, <4 x i16> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_4h
-; CHECK: st2.4h
-; EXYNOS-LABEL: st2_4h
-; EXYNOS: zip1.4h
-; EXYNOS: zip2.4h
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_4h:
+; SD-CHECK: st2.4h { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_4h:
+; GI-CHECK: st2.4h { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_4h:
+; EXYNOS: zip1.4h v2, v0, v1
+; EXYNOS: zip2.4h v0, v0, v1
+; EXYNOS: stp d2, d0, [x0]
call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> %A, <4 x i16> %B, ptr %P)
ret void
}
define void @st3_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_4h
-; CHECK: st3.4h
+; CHECK-LABEL: st3_4h:
+; CHECK: st3.4h { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %P)
ret void
}
define void @st4_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_4h
-; CHECK: st4.4h
-; EXYNOS-LABEL: st4_4h
-; EXYNOS: zip1.4h
-; EXYNOS: zip2.4h
-; EXYNOS: zip1.4h
-; EXYNOS: zip2.4h
-; EXYNOS: zip1.4h
-; EXYNOS: zip2.4h
-; EXYNOS: stp
-; EXYNOS: zip1.4h
-; EXYNOS: zip2.4h
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_4h:
+; SD-CHECK: st4.4h { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_4h:
+; GI-CHECK: st4.4h { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_4h:
+; EXYNOS: zip1.4h v4, v0, v2
+; EXYNOS: zip2.4h v0, v0, v2
+; EXYNOS: zip1.4h v2, v1, v3
+; EXYNOS: zip2.4h v1, v1, v3
+; EXYNOS: zip1.4h v3, v4, v2
+; EXYNOS: zip2.4h v2, v4, v2
+; EXYNOS: stp d3, d2, [x0]
+; EXYNOS: zip1.4h v4, v0, v1
+; EXYNOS: zip2.4h v0, v0, v1
+; EXYNOS: stp d4, d0, [x0, #16]
call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %P)
ret void
}
@@ -722,37 +767,45 @@ declare void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, pt
declare void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, ptr) nounwind readonly
define void @st2_8h(<8 x i16> %A, <8 x i16> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_8h
-; CHECK: st2.8h
-; EXYNOS-LABEL: st2_8h
-; EXYNOS: zip1.8h
-; EXYNOS: zip2.8h
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_8h:
+; SD-CHECK: st2.8h { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_8h:
+; GI-CHECK: st2.8h { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_8h:
+; EXYNOS: zip1.8h v2, v0, v1
+; EXYNOS: zip2.8h v0, v0, v1
+; EXYNOS: stp q2, q0, [x0]
call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> %A, <8 x i16> %B, ptr %P)
ret void
}
define void @st3_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_8h
-; CHECK: st3.8h
+; CHECK-LABEL: st3_8h:
+; CHECK: st3.8h { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %P)
ret void
}
define void @st4_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_8h
-; CHECK: st4.8h
-; EXYNOS-LABEL: st4_8h
-; EXYNOS: zip1.8h
-; EXYNOS: zip2.8h
-; EXYNOS: zip1.8h
-; EXYNOS: zip2.8h
-; EXYNOS: zip1.8h
-; EXYNOS: zip2.8h
-; EXYNOS: stp
-; EXYNOS: zip1.8h
-; EXYNOS: zip2.8h
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_8h:
+; SD-CHECK: st4.8h { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_8h:
+; GI-CHECK: st4.8h { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_8h:
+; EXYNOS: zip1.8h v4, v0, v2
+; EXYNOS: zip2.8h v0, v0, v2
+; EXYNOS: zip1.8h v2, v1, v3
+; EXYNOS: zip2.8h v1, v1, v3
+; EXYNOS: zip1.8h v3, v4, v2
+; EXYNOS: zip2.8h v2, v4, v2
+; EXYNOS: stp q3, q2, [x0]
+; EXYNOS: zip1.8h v4, v0, v1
+; EXYNOS: zip2.8h v0, v0, v1
+; EXYNOS: stp q4, q0, [x0, #32]
call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %P)
ret void
}
@@ -762,37 +815,45 @@ declare void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, pt
declare void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, ptr) nounwind readonly
define void @st2_2s(<2 x i32> %A, <2 x i32> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_2s
-; CHECK: st2.2s
-; EXYNOS-LABEL: st2_2s
-; EXYNOS: zip1.2s
-; EXYNOS: zip2.2s
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_2s:
+; SD-CHECK: st2.2s { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_2s:
+; GI-CHECK: st2.2s { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_2s:
+; EXYNOS: zip1.2s v2, v0, v1
+; EXYNOS: zip2.2s v0, v0, v1
+; EXYNOS: stp d2, d0, [x0]
call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> %A, <2 x i32> %B, ptr %P)
ret void
}
define void @st3_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_2s
-; CHECK: st3.2s
+; CHECK-LABEL: st3_2s:
+; CHECK: st3.2s { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %P)
ret void
}
define void @st4_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_2s
-; CHECK: st4.2s
-; EXYNOS-LABEL: st4_2s
-; EXYNOS: zip1.2s
-; EXYNOS: zip2.2s
-; EXYNOS: zip1.2s
-; EXYNOS: zip2.2s
-; EXYNOS: zip1.2s
-; EXYNOS: zip2.2s
-; EXYNOS: stp
-; EXYNOS: zip1.2s
-; EXYNOS: zip2.2s
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_2s:
+; SD-CHECK: st4.2s { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_2s:
+; GI-CHECK: st4.2s { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_2s:
+; EXYNOS: zip1.2s v4, v0, v2
+; EXYNOS: zip2.2s v0, v0, v2
+; EXYNOS: zip1.2s v2, v1, v3
+; EXYNOS: zip2.2s v1, v1, v3
+; EXYNOS: zip1.2s v3, v4, v2
+; EXYNOS: zip2.2s v2, v4, v2
+; EXYNOS: stp d3, d2, [x0]
+; EXYNOS: zip1.2s v4, v0, v1
+; EXYNOS: zip2.2s v0, v0, v1
+; EXYNOS: stp d4, d0, [x0, #16]
call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %P)
ret void
}
@@ -802,37 +863,45 @@ declare void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, pt
declare void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, ptr) nounwind readonly
define void @st2_4s(<4 x i32> %A, <4 x i32> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_4s
-; CHECK: st2.4s
-; EXYNOS-LABEL: st2_4s
-; EXYNOS: zip1.4s
-; EXYNOS: zip2.4s
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_4s:
+; SD-CHECK: st2.4s { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_4s:
+; GI-CHECK: st2.4s { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_4s:
+; EXYNOS: zip1.4s v2, v0, v1
+; EXYNOS: zip2.4s v0, v0, v1
+; EXYNOS: stp q2, q0, [x0]
call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %A, <4 x i32> %B, ptr %P)
ret void
}
define void @st3_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_4s
-; CHECK: st3.4s
+; CHECK-LABEL: st3_4s:
+; CHECK: st3.4s { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %P)
ret void
}
define void @st4_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_4s
-; CHECK: st4.4s
-; EXYNOS-LABEL: st4_4s
-; EXYNOS: zip1.4s
-; EXYNOS: zip2.4s
-; EXYNOS: zip1.4s
-; EXYNOS: zip2.4s
-; EXYNOS: zip1.4s
-; EXYNOS: zip2.4s
-; EXYNOS: stp
-; EXYNOS: zip1.4s
-; EXYNOS: zip2.4s
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_4s:
+; SD-CHECK: st4.4s { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_4s:
+; GI-CHECK: st4.4s { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_4s:
+; EXYNOS: zip1.4s v4, v0, v2
+; EXYNOS: zip2.4s v0, v0, v2
+; EXYNOS: zip1.4s v2, v1, v3
+; EXYNOS: zip2.4s v1, v1, v3
+; EXYNOS: zip1.4s v3, v4, v2
+; EXYNOS: zip2.4s v2, v4, v2
+; EXYNOS: stp q3, q2, [x0]
+; EXYNOS: zip1.4s v4, v0, v1
+; EXYNOS: zip2.4s v0, v0, v1
+; EXYNOS: stp q4, q0, [x0, #32]
call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %P)
ret void
}
@@ -843,22 +912,22 @@ declare void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, <4
; If there's only one element, st2/3/4 don't make much sense, stick to st1.
define void @st2_1d(<1 x i64> %A, <1 x i64> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_1d
-; CHECK: st1.1d
+; CHECK-LABEL: st2_1d:
+; CHECK: st1.1d { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> %A, <1 x i64> %B, ptr %P)
ret void
}
define void @st3_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_1d
-; CHECK: st1.1d
+; CHECK-LABEL: st3_1d:
+; CHECK: st1.1d { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %P)
ret void
}
define void @st4_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_1d
-; CHECK: st1.1d
+; CHECK-LABEL: st4_1d:
+; CHECK: st1.1d { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %P)
ret void
}
@@ -868,37 +937,45 @@ declare void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, pt
declare void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, ptr) nounwind readonly
define void @st2_2d(<2 x i64> %A, <2 x i64> %B, ptr %P) nounwind {
-; CHECK-LABEL: st2_2d
-; CHECK: st2.2d
-; EXYNOS-LABEL: st2_2d
-; EXYNOS: zip1.2d
-; EXYNOS: zip2.2d
-; EXYNOS: stp
+; SD-CHECK-LABEL: st2_2d:
+; SD-CHECK: st2.2d { v0, v1 }, [x0]
+;
+; GI-CHECK-LABEL: st2_2d:
+; GI-CHECK: st2.2d { v0, v1 }, [x0]
+;
+; EXYNOS-LABEL: st2_2d:
+; EXYNOS: zip1.2d v2, v0, v1
+; EXYNOS: zip2.2d v0, v0, v1
+; EXYNOS: stp q2, q0, [x0]
call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> %A, <2 x i64> %B, ptr %P)
ret void
}
define void @st3_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %P) nounwind {
-; CHECK-LABEL: st3_2d
-; CHECK: st3.2d
+; CHECK-LABEL: st3_2d:
+; CHECK: st3.2d { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %P)
ret void
}
define void @st4_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %P) nounwind {
-; CHECK-LABEL: st4_2d
-; CHECK: st4.2d
-; EXYNOS-LABEL: st4_2d
-; EXYNOS: zip1.2d
-; EXYNOS: zip2.2d
-; EXYNOS: zip1.2d
-; EXYNOS: zip2.2d
-; EXYNOS: zip1.2d
-; EXYNOS: zip2.2d
-; EXYNOS: stp
-; EXYNOS: zip1.2d
-; EXYNOS: zip2.2d
-; EXYNOS: stp
+; SD-CHECK-LABEL: st4_2d:
+; SD-CHECK: st4.2d { v0, v1, v2, v3 }, [x0]
+;
+; GI-CHECK-LABEL: st4_2d:
+; GI-CHECK: st4.2d { v0, v1, v2, v3 }, [x0]
+;
+; EXYNOS-LABEL: st4_2d:
+; EXYNOS: zip1.2d v4, v0, v2
+; EXYNOS: zip2.2d v0, v0, v2
+; EXYNOS: zip1.2d v2, v1, v3
+; EXYNOS: zip2.2d v1, v1, v3
+; EXYNOS: zip1.2d v3, v4, v2
+; EXYNOS: zip2.2d v2, v4, v2
+; EXYNOS: stp q3, q2, [x0]
+; EXYNOS: zip1.2d v4, v0, v1
+; EXYNOS: zip2.2d v0, v0, v1
+; EXYNOS: stp q4, q0, [x0, #32]
call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %P)
ret void
}
@@ -916,42 +993,42 @@ declare void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double>, <1 x double>, ptr)
define void @st1_x2_v8i8(<8 x i8> %A, <8 x i8> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v8i8:
-; CHECK: st1.8b { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.8b { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> %A, <8 x i8> %B, ptr %addr)
ret void
}
define void @st1_x2_v4i16(<4 x i16> %A, <4 x i16> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v4i16:
-; CHECK: st1.4h { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4h { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> %A, <4 x i16> %B, ptr %addr)
ret void
}
define void @st1_x2_v2i32(<2 x i32> %A, <2 x i32> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v2i32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2s { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32> %A, <2 x i32> %B, ptr %addr)
ret void
}
define void @st1_x2_v2f32(<2 x float> %A, <2 x float> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v2f32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2s { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float> %A, <2 x float> %B, ptr %addr)
ret void
}
define void @st1_x2_v1i64(<1 x i64> %A, <1 x i64> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v1i64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.1d { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> %A, <1 x i64> %B, ptr %addr)
ret void
}
define void @st1_x2_v1f64(<1 x double> %A, <1 x double> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v1f64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.1d { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double> %A, <1 x double> %B, ptr %addr)
ret void
}
@@ -965,42 +1042,42 @@ declare void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double>, <2 x double>, ptr)
define void @st1_x2_v16i8(<16 x i8> %A, <16 x i8> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v16i8:
-; CHECK: st1.16b { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.16b { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> %A, <16 x i8> %B, ptr %addr)
ret void
}
define void @st1_x2_v8i16(<8 x i16> %A, <8 x i16> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v8i16:
-; CHECK: st1.8h { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.8h { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> %A, <8 x i16> %B, ptr %addr)
ret void
}
define void @st1_x2_v4i32(<4 x i32> %A, <4 x i32> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v4i32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4s { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32> %A, <4 x i32> %B, ptr %addr)
ret void
}
define void @st1_x2_v4f32(<4 x float> %A, <4 x float> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v4f32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4s { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float> %A, <4 x float> %B, ptr %addr)
ret void
}
define void @st1_x2_v2i64(<2 x i64> %A, <2 x i64> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v2i64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2d { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> %A, <2 x i64> %B, ptr %addr)
ret void
}
define void @st1_x2_v2f64(<2 x double> %A, <2 x double> %B, ptr %addr) {
; CHECK-LABEL: st1_x2_v2f64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2d { v0, v1 }, [x0]
call void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double> %A, <2 x double> %B, ptr %addr)
ret void
}
@@ -1014,42 +1091,42 @@ declare void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double>, <1 x double>, <1 x
define void @st1_x3_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v8i8:
-; CHECK: st1.8b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.8b { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, ptr %addr)
ret void
}
define void @st1_x3_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v4i16:
-; CHECK: st1.4h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4h { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, ptr %addr)
ret void
}
define void @st1_x3_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v2i32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2s { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, ptr %addr)
ret void
}
define void @st1_x3_v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v2f32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2s { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float> %A, <2 x float> %B, <2 x float> %C, ptr %addr)
ret void
}
define void @st1_x3_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v1i64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.1d { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, ptr %addr)
ret void
}
define void @st1_x3_v1f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v1f64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.1d { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double> %A, <1 x double> %B, <1 x double> %C, ptr %addr)
ret void
}
@@ -1063,42 +1140,42 @@ declare void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double>, <2 x double>, <2 x
define void @st1_x3_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v16i8:
-; CHECK: st1.16b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.16b { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %addr)
ret void
}
define void @st1_x3_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v8i16:
-; CHECK: st1.8h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.8h { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, ptr %addr)
ret void
}
define void @st1_x3_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v4i32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4s { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, ptr %addr)
ret void
}
define void @st1_x3_v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v4f32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4s { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float> %A, <4 x float> %B, <4 x float> %C, ptr %addr)
ret void
}
define void @st1_x3_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v2i64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2d { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, ptr %addr)
ret void
}
define void @st1_x3_v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, ptr %addr) {
; CHECK-LABEL: st1_x3_v2f64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2d { v0, v1, v2 }, [x0]
call void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double> %A, <2 x double> %B, <2 x double> %C, ptr %addr)
ret void
}
@@ -1113,42 +1190,42 @@ declare void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double>, <1 x double>, <1 x
define void @st1_x4_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v8i8:
-; CHECK: st1.8b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.8b { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %addr)
ret void
}
define void @st1_x4_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v4i16:
-; CHECK: st1.4h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4h { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %addr)
ret void
}
define void @st1_x4_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v2i32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2s { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %addr)
ret void
}
define void @st1_x4_v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v2f32:
-; CHECK: st1.2s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2s { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float> %A, <2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %addr)
ret void
}
define void @st1_x4_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v1i64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.1d { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %addr)
ret void
}
define void @st1_x4_v1f64(<1 x double> %A, <1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v1f64:
-; CHECK: st1.1d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.1d { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double> %A, <1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %addr)
ret void
}
@@ -1162,42 +1239,42 @@ declare void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double>, <2 x double>, <2 x
define void @st1_x4_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v16i8:
-; CHECK: st1.16b { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.16b { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %addr)
ret void
}
define void @st1_x4_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v8i16:
-; CHECK: st1.8h { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.8h { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %addr)
ret void
}
define void @st1_x4_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v4i32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4s { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %addr)
ret void
}
define void @st1_x4_v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v4f32:
-; CHECK: st1.4s { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.4s { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float> %A, <4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %addr)
ret void
}
define void @st1_x4_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v2i64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2d { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %addr)
ret void
}
define void @st1_x4_v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %addr) {
; CHECK-LABEL: st1_x4_v2f64:
-; CHECK: st1.2d { {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} }, [x0]
+; CHECK: st1.2d { v0, v1, v2, v3 }, [x0]
call void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double> %A, <2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %addr)
ret void
}
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