[llvm] 6a63abc - [RISCV] Use GPRMemZeroOffset instead of GPRMem in RISCVInstrInfoVPseudos.td. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 9 17:13:03 PDT 2025
Author: Craig Topper
Date: 2025-04-09T17:07:01-07:00
New Revision: 6a63abce7b54076015b52d6b99c51eb04d2763f6
URL: https://github.com/llvm/llvm-project/commit/6a63abce7b54076015b52d6b99c51eb04d2763f6
DIFF: https://github.com/llvm/llvm-project/commit/6a63abce7b54076015b52d6b99c51eb04d2763f6.diff
LOG: [RISCV] Use GPRMemZeroOffset instead of GPRMem in RISCVInstrInfoVPseudos.td. NFC
The distinction between GPRMem and GPRMemZeroOffset only matters
for parsing which doesn't apply to pseudos.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index d0e0ed91af7d8..5edcfdf2654a4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -783,7 +783,7 @@ class VPseudoUSLoadNoMask<VReg RetClass,
int EEW,
DAGOperand sewop = sew> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sewop:$sew,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew,
vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -800,7 +800,7 @@ class VPseudoUSLoadMask<VReg RetClass,
int EEW> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMem:$rs1,
+ GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -818,7 +818,7 @@ class VPseudoUSLoadMask<VReg RetClass,
class VPseudoUSLoadFFNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
- (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -835,7 +835,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
int EEW> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
(ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMem:$rs1,
+ GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -853,7 +853,7 @@ class VPseudoUSLoadFFMask<VReg RetClass,
class VPseudoSLoadNoMask<VReg RetClass,
int EEW> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -870,7 +870,7 @@ class VPseudoSLoadMask<VReg RetClass,
int EEW> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMem:$rs1, GPR:$rs2,
+ GPRMemZeroOffset:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLE</*Masked*/1, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -893,7 +893,7 @@ class VPseudoILoadNoMask<VReg RetClass,
bit EarlyClobber,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -916,7 +916,7 @@ class VPseudoILoadMask<VReg RetClass,
bits<2> TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$passthru,
- GPRMem:$rs1, IdxClass:$rs2,
+ GPRMemZeroOffset:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -936,7 +936,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
int EEW,
DAGOperand sewop = sew> :
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sewop:$sew), []>,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -949,7 +949,7 @@ class VPseudoUSStoreNoMask<VReg StClass,
class VPseudoUSStoreMask<VReg StClass,
int EEW> :
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
@@ -964,7 +964,7 @@ class VPseudoUSStoreMask<VReg StClass,
class VPseudoSStoreNoMask<VReg StClass,
int EEW> :
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -978,7 +978,7 @@ class VPseudoSStoreNoMask<VReg StClass,
class VPseudoSStoreMask<VReg StClass,
int EEW> :
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSE</*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -1329,7 +1329,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl,
sew:$sew),[]>,
RISCVVPseudo,
RISCVVSX</*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1343,7 +1343,7 @@ class VPseudoIStoreNoMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
class VPseudoIStoreMask<VReg StClass, VReg IdxClass, int EEW, bits<3> LMUL,
bit Ordered>:
Pseudo<(outs),
- (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2,
+ (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2,
VMaskOp:$vm, AVL:$vl, sew:$sew),[]>,
RISCVVPseudo,
RISCVVSX</*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1598,7 +1598,7 @@ class VPseudoUSSegLoadNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -1615,7 +1615,7 @@ class VPseudoUSSegLoadMask<VReg RetClass,
int EEW,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
+ (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -1634,7 +1634,7 @@ class VPseudoUSSegLoadFFNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
Pseudo<(outs RetClass:$rd, GPR:$vl),
- (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl,
+ (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -1651,7 +1651,7 @@ class VPseudoUSSegLoadFFMask<VReg RetClass,
int EEW,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd, GPR:$vl),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
+ (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/1, /*Strided*/0, /*FF*/1, !logtwo(EEW), VLMul> {
@@ -1670,7 +1670,7 @@ class VPseudoSSegLoadNoMask<VReg RetClass,
int EEW,
bits<4> NF> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl,
+ (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/1, /*FF*/0, !logtwo(EEW), VLMul> {
@@ -1687,7 +1687,7 @@ class VPseudoSSegLoadMask<VReg RetClass,
int EEW,
bits<4> NF> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
+ (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
vec_policy:$policy), []>,
RISCVVPseudo,
@@ -1710,7 +1710,7 @@ class VPseudoISegLoadNoMask<VReg RetClass,
bits<4> NF,
bit Ordered> :
Pseudo<(outs RetClass:$rd),
- (ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl,
+ (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl,
sew:$sew, vec_policy:$policy), []>,
RISCVVPseudo,
RISCVVLXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1732,7 +1732,7 @@ class VPseudoISegLoadMask<VReg RetClass,
bits<4> NF,
bit Ordered> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
- (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMem:$rs1,
+ (ins GetVRegNoV0<RetClass>.R:$passthru, GPRMemZeroOffset:$rs1,
IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew,
vec_policy:$policy), []>,
RISCVVPseudo,
@@ -1754,7 +1754,7 @@ class VPseudoUSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/0, !logtwo(EEW), VLMul> {
let mayLoad = 0;
@@ -1768,7 +1768,7 @@ class VPseudoUSSegStoreMask<VReg ValClass,
int EEW,
bits<4> NF> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/0, !logtwo(EEW), VLMul> {
@@ -1784,7 +1784,7 @@ class VPseudoSSegStoreNoMask<VReg ValClass,
int EEW,
bits<4> NF> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1, GPR:$offset,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/0, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -1799,7 +1799,7 @@ class VPseudoSSegStoreMask<VReg ValClass,
int EEW,
bits<4> NF> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSSEG<NF, /*Masked*/1, /*Strided*/1, !logtwo(EEW), VLMul> {
@@ -1818,7 +1818,7 @@ class VPseudoISegStoreNoMask<VReg ValClass,
bits<4> NF,
bit Ordered> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSXSEG<NF, /*Masked*/0, Ordered, !logtwo(EEW), VLMul, LMUL> {
@@ -1836,7 +1836,7 @@ class VPseudoISegStoreMask<VReg ValClass,
bits<4> NF,
bit Ordered> :
Pseudo<(outs),
- (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index,
+ (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index,
VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
RISCVVPseudo,
RISCVVSXSEG<NF, /*Masked*/1, Ordered, !logtwo(EEW), VLMul, LMUL> {
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