[llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/include/llvm/CodeGen/MachineScheduler.h llvm/lib/CodeGen/MachineScheduler.cpp llvm/lib/Target/SystemZ/SystemZElimCompare.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/lib/Target/SystemZ/SystemZInstrInfo.h llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp llvm/lib/Target/SystemZ/SystemZMachineScheduler.h llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/lib/Target/SystemZ/SystemZTargetMachine.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 54a2adcc4..4dc11c409 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -2150,18 +2150,18 @@ bool SystemZInstrInfo::isLoadAndTestAsCmp(const MachineInstr &MI) const {
   return (MI.getOpcode() == SystemZ::LTEBR ||
           MI.getOpcode() == SystemZ::LTDBR ||
           MI.getOpcode() == SystemZ::LTXBR) &&
-    MI.getOperand(0).isDead();
+         MI.getOperand(0).isDead();
 }
 
 bool SystemZInstrInfo::isCompareZero(const MachineInstr &Compare) const {
   if (isLoadAndTestAsCmp(Compare))
     return true;
   return Compare.isCompare() && Compare.getNumExplicitOperands() == 2 &&
-    Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
+         Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
 }
 
-unsigned SystemZInstrInfo::
-getCompareSourceReg(const MachineInstr &Compare) const {
+unsigned
+SystemZInstrInfo::getCompareSourceReg(const MachineInstr &Compare) const {
   unsigned reg = 0;
   if (Compare.isCompare())
     reg = Compare.getOperand(0).getReg();
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
index 85376ec70..1f5c1be06 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
@@ -109,8 +109,8 @@ void SystemZPreRASchedStrategy::initializeStoresGroup() {
         return;
       if (IsStore)
         StoresGroup.insert(SU);
-    }
-    else if (IsStore && !StoresGroup.empty() && SU->getDepth() == CurrMaxDepth) {
+    } else if (IsStore && !StoresGroup.empty() &&
+               SU->getDepth() == CurrMaxDepth) {
       // The group members should all have the same opcode.
       if ((*StoresGroup.begin())->getInstr()->getOpcode() != MI->getOpcode()) {
         StoresGroup.clear();
@@ -142,9 +142,8 @@ static int biasPhysRegExtra(const SUnit *SU) {
   return 0;
 }
 
-int SystemZPreRASchedStrategy::
-computeSULivenessScore(SchedCandidate &C, ScheduleDAGMILive *DAG,
-                       SchedBoundary *Zone) const {
+int SystemZPreRASchedStrategy::computeSULivenessScore(
+    SchedCandidate &C, ScheduleDAGMILive *DAG, SchedBoundary *Zone) const {
   // Not all data deps are modelled around the SUnit - some data edges near
   // boundaries are missing: Look directly at the MI operands instead.
   const SUnit *SU = C.SU;
@@ -246,22 +245,24 @@ bool SystemZPreRASchedStrategy::tryCandidate(SchedCandidate &Cand,
       return TryCand.Reason != NoCand;
 
     // Don't extend the scheduled latency.
-    if (ShouldReduceLatency && TryCand.SU->getHeight() != Cand.SU->getHeight() &&
+    if (ShouldReduceLatency &&
+        TryCand.SU->getHeight() != Cand.SU->getHeight() &&
         (std::max(TryCand.SU->getHeight(), Cand.SU->getHeight()) >
          Zone->getScheduledLatency())) {
-      unsigned HigherSUDepth = TryCand.SU->getHeight() < Cand.SU->getHeight() ?
-        Cand.SU->getDepth() : TryCand.SU->getDepth();
+      unsigned HigherSUDepth = TryCand.SU->getHeight() < Cand.SU->getHeight()
+                                   ? Cand.SU->getDepth()
+                                   : TryCand.SU->getDepth();
       if (HigherSUDepth != getRemLat(Zone) &&
-          tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(),
-                  TryCand, Cand, GenericSchedulerBase::BotHeightReduce)) {
+          tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), TryCand, Cand,
+                  GenericSchedulerBase::BotHeightReduce)) {
         return TryCand.Reason != NoCand;
       }
     }
   }
 
   // Weak edges are for clustering and other constraints.
-  if (tryLess(TryCand.SU->WeakSuccsLeft, Cand.SU->WeakSuccsLeft,
-              TryCand, Cand, Weak))
+  if (tryLess(TryCand.SU->WeakSuccsLeft, Cand.SU->WeakSuccsLeft, TryCand, Cand,
+              Weak))
     return TryCand.Reason != NoCand;
 
   // Fall through to original instruction order.
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
index 6219e7083..cd306e8e2 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.h
@@ -70,7 +70,7 @@ class SystemZPreRASchedStrategy : public GenericScheduler {
   unsigned getRemLat(SchedBoundary *Zone) const;
 
   // A large group of stores at the bottom is spread upwards.
-  std::set<const SUnit*> StoresGroup;
+  std::set<const SUnit *> StoresGroup;
   bool FirstStoreInGroupScheduled;
   void initializeStoresGroup();
 
@@ -86,7 +86,8 @@ protected:
                     SchedBoundary *Zone) const override;
 
 public:
-  SystemZPreRASchedStrategy(const MachineSchedContext *C) : GenericScheduler(C) {
+  SystemZPreRASchedStrategy(const MachineSchedContext *C)
+      : GenericScheduler(C) {
     initializePrioRegClasses(C->MF->getRegInfo().getTargetRegisterInfo());
   }
 
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
index 70460c619..5a72002aa 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
@@ -212,7 +212,7 @@ SystemZTargetMachine::getSubtargetImpl(const Function &F) const {
 }
 
 ScheduleDAGInstrs *
-SystemZTargetMachine::createMachineScheduler(MachineSchedContext *C) const  {
+SystemZTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
   // Use GenericScheduler if requested on CL or for Z10, which has no sched
   // model.
   if (GenericSched ||
@@ -220,7 +220,7 @@ SystemZTargetMachine::createMachineScheduler(MachineSchedContext *C) const  {
     return nullptr;
 
   ScheduleDAGMILive *DAG =
-    new ScheduleDAGMILive(C, std::make_unique<SystemZPreRASchedStrategy>(C));
+      new ScheduleDAGMILive(C, std::make_unique<SystemZPreRASchedStrategy>(C));
   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
   return DAG;
 }

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https://github.com/llvm/llvm-project/pull/135076