[llvm] fix a assert on the PR 125883 (PR #135056)

[zhijian lin via llvm-commits]

https://github.com/diggerlin updated https://github.com/llvm/llvm-project/pull/135056

>From e4b240ea12ecc7cb250ece11f9a39ab2d05b0b92 Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Wed, 9 Apr 2025 17:31:36 +0000
Subject: [PATCH 1/2] fix a assert on the PR 125883

---
 .../SelectionDAG/LegalizeFloatTypes.cpp       |  1 +
 llvm/test/CodeGen/RISCV/pr125883.ll           | 19 +++++++++++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/pr125883.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 5ed83060e150e..6493e0e6583f0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -165,6 +165,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
     case ISD::STRICT_UINT_TO_FP:
     case ISD::SINT_TO_FP:
     case ISD::UINT_TO_FP:  R = SoftenFloatRes_XINT_TO_FP(N); break;
+    case ISD::POISON:
     case ISD::UNDEF:       R = SoftenFloatRes_UNDEF(N); break;
     case ISD::VAARG:       R = SoftenFloatRes_VAARG(N); break;
     case ISD::VECREDUCE_FADD:
diff --git a/llvm/test/CodeGen/RISCV/pr125883.ll b/llvm/test/CodeGen/RISCV/pr125883.ll
new file mode 100644
index 0000000000000..f2da05c660be6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr125883.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -mtriple=riscv32  | FileCheck %s
+
+define void @b(ptr %p1)  {
+; CHECK:        .cfi_startproc
+; CHECK-NEXT: # %bb.0:                                # %entry
+; CHECK-NEXT:   sb      zero, 7(a0)
+; CHECK-NEXT:   sb      zero, 6(a0)
+; CHECK-NEXT:   sb      zero, 5(a0)
+; CHECK-NEXT:   sb      a0, 4(a0)
+; CHECK-NEXT:   sb      zero, 3(a0)
+; CHECK-NEXT:   sb      zero, 2(a0)
+; CHECK-NEXT:   sb      zero, 1(a0)
+; CHECK-NEXT:   sb      a0, 0(a0)
+; CHECK-NEXT:   ret
+
+entry:
+  store volatile double poison, ptr %p1, align 1
+  ret void
+}

>From a7456d0a271085d1c18efaaacdca5a130c76538f Mon Sep 17 00:00:00 2001
From: zhijian <zhijian at ca.ibm.com>
Date: Wed, 9 Apr 2025 17:33:46 +0000
Subject: [PATCH 2/2] change test case name

---
 llvm/test/CodeGen/RISCV/{pr125883.ll => pr135056.ll} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename llvm/test/CodeGen/RISCV/{pr125883.ll => pr135056.ll} (100%)

diff --git a/llvm/test/CodeGen/RISCV/pr125883.ll b/llvm/test/CodeGen/RISCV/pr135056.ll
similarity index 100%
rename from llvm/test/CodeGen/RISCV/pr125883.ll
rename to llvm/test/CodeGen/RISCV/pr135056.ll