[llvm] [LV] Reduce register usage for scaled reductions (PR #133090)

[Sander de Smalen via llvm-commits]

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@@ -5028,10 +5041,19 @@ calculateRegisterUsage(VPlan &Plan, ArrayRef<ElementCount> VFs,
           // even in the scalar case.
           RegUsage[ClassID] += 1;
         } else {
+          // The output from scaled phis and scaled reductions actually has
+          // fewer lanes than the VF.
+          unsigned ScaleFactor = getVFScaleFactor(R);
+          ElementCount VF = VFs[J].divideCoefficientBy(ScaleFactor);
+          LLVM_DEBUG(if (VF != VFs[J]) {
+            dbgs() << "LV(REG): Scaled down VF from " << VFs[J] << " to " << VF
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sdesmalen-arm wrote:

nit: for the tests that check the debug output, can a check for this line be added?

https://github.com/llvm/llvm-project/pull/133090