[llvm] [MIPS] Add FeatureMSA to i6400 and i6500 cores (PR #134985)

[Mallikarjuna Gouda via llvm-commits]

https://github.com/mgoudar created https://github.com/llvm/llvm-project/pull/134985

Enable 'FeatureMSA' for MIPS i6400 and i6500 cpu.

MIPS i6400 and i6500 cores implements MSA (MIPS SIMD ARCHITECTURE) by default.

>From b6722de44a8bac9210a70763f4314e51afdf51f3 Mon Sep 17 00:00:00 2001
From: Mallikarjuna Gouda <mgouda at mips.com>
Date: Tue, 1 Apr 2025 12:35:27 +0530
Subject: [PATCH] [MIPS] Add FeatureMSA to i6400 and i6500 cores

i6400 and i6500 cores support MIPS SIMD Architecture (MSA) instructions
---
 llvm/lib/Target/Mips/Mips.td        |  4 +-
 llvm/test/CodeGen/Mips/msa/i6500.ll | 64 +++++++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/msa/i6500.ll

diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
 // same CPU architecture.
 def ImplI6400
     : SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
-                       "MIPS I6400 Processor", [FeatureMips64r6]>;
+                       "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 def ImplI6500
     : SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
-                       "MIPS I6500 Processor", [FeatureMips64r6]>;
+                       "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
 
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, MipsGenericModel, Features>;
diff --git a/llvm/test/CodeGen/Mips/msa/i6500.ll b/llvm/test/CodeGen/Mips/msa/i6500.ll
new file mode 100644
index 0000000000000..fb2bc012c1ddf
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/msa/i6500.ll
@@ -0,0 +1,64 @@
+; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
+
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS32
+; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
+; RUN:   FileCheck %s --check-prefix=MIPS64
+
+define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
+  ret i32 %0
+}
+
+declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
+
+; MIPS32: llvm_mips_lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size llvm_mips_lsa_test
+
+define i32 @lsa_test(i32 %a, i32 %b) nounwind {
+entry:
+  %0 = shl i32 %b, 2
+  %1 = add i32 %a, %0
+  ret i32 %1
+}
+
+; MIPS32: lsa_test:
+; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS32: .size lsa_test
+
+define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
+  ret i64 %0
+}
+
+declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
+
+; MIPS64: llvm_mips_dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size llvm_mips_dlsa_test
+
+define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
+entry:
+  %0 = shl i64 %b, 2
+  %1 = add i64 %a, %0
+  ret i64 %1
+}
+
+; MIPS64: dlsa_test:
+; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
+; MIPS64: .size dlsa_test