[llvm] e6e0f5f - [RISCV][test] Add tests for subtraction if above threshold
Piotr Fusik via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 8 23:09:22 PDT 2025
Author: Piotr Fusik
Date: 2025-04-09T08:08:41+02:00
New Revision: e6e0f5f17aa3c995709fc7623a0abbb5a32e4af5
URL: https://github.com/llvm/llvm-project/commit/e6e0f5f17aa3c995709fc7623a0abbb5a32e4af5
DIFF: https://github.com/llvm/llvm-project/commit/e6e0f5f17aa3c995709fc7623a0abbb5a32e4af5.diff
LOG: [RISCV][test] Add tests for subtraction if above threshold
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zbb.ll
llvm/test/CodeGen/RISCV/rv64zbb.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
index 90a8eadb3f974..8103ddcc427cd 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -1479,3 +1479,189 @@ entry:
%cmp = icmp ne i32 %popcnt, 1
ret i1 %cmp
}
+
+define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sub_if_uge_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: zext.b a2, a1
+; CHECK-NEXT: zext.b a3, a0
+; CHECK-NEXT: sltu a2, a3, a2
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i8 %x, %y
+ %select = select i1 %cmp, i8 0, i8 %y
+ %sub = sub nuw i8 %x, %select
+ ret i8 %sub
+}
+
+define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
+; RV32I-LABEL: sub_if_uge_i16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a2, 16
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a3, a1, a2
+; RV32I-NEXT: and a2, a0, a2
+; RV32I-NEXT: sltu a2, a2, a3
+; RV32I-NEXT: addi a2, a2, -1
+; RV32I-NEXT: and a1, a2, a1
+; RV32I-NEXT: sub a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32ZBB-LABEL: sub_if_uge_i16:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: zext.h a2, a1
+; RV32ZBB-NEXT: zext.h a3, a0
+; RV32ZBB-NEXT: sltu a2, a3, a2
+; RV32ZBB-NEXT: addi a2, a2, -1
+; RV32ZBB-NEXT: and a1, a2, a1
+; RV32ZBB-NEXT: sub a0, a0, a1
+; RV32ZBB-NEXT: ret
+ %cmp = icmp ult i16 %x, %y
+ %select = select i1 %cmp, i16 0, i16 %y
+ %sub = sub nuw i16 %x, %select
+ ret i16 %sub
+}
+
+define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a2, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB52_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: j .LBB52_3
+; CHECK-NEXT: .LBB52_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: .LBB52_3:
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: sub a1, a1, a3
+; CHECK-NEXT: sub a1, a1, a4
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, %y
+ %select = select i1 %cmp, i64 0, i64 %y
+ %sub = sub nuw i64 %x, %select
+ ret i64 %sub
+}
+
+define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lw a7, 4(a2)
+; CHECK-NEXT: lw a6, 8(a2)
+; CHECK-NEXT: lw t0, 12(a2)
+; CHECK-NEXT: lw a4, 12(a1)
+; CHECK-NEXT: lw a3, 4(a1)
+; CHECK-NEXT: lw a5, 8(a1)
+; CHECK-NEXT: beq a4, t0, .LBB53_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu t1, a4, t0
+; CHECK-NEXT: j .LBB53_3
+; CHECK-NEXT: .LBB53_2:
+; CHECK-NEXT: sltu t1, a5, a6
+; CHECK-NEXT: .LBB53_3:
+; CHECK-NEXT: lw a2, 0(a2)
+; CHECK-NEXT: lw a1, 0(a1)
+; CHECK-NEXT: beq a3, a7, .LBB53_5
+; CHECK-NEXT: # %bb.4:
+; CHECK-NEXT: sltu t2, a3, a7
+; CHECK-NEXT: j .LBB53_6
+; CHECK-NEXT: .LBB53_5:
+; CHECK-NEXT: sltu t2, a1, a2
+; CHECK-NEXT: .LBB53_6:
+; CHECK-NEXT: xor t3, a4, t0
+; CHECK-NEXT: xor t4, a5, a6
+; CHECK-NEXT: or t3, t4, t3
+; CHECK-NEXT: beqz t3, .LBB53_8
+; CHECK-NEXT: # %bb.7:
+; CHECK-NEXT: mv t2, t1
+; CHECK-NEXT: .LBB53_8:
+; CHECK-NEXT: addi t2, t2, -1
+; CHECK-NEXT: and t1, t2, t0
+; CHECK-NEXT: and t0, t2, a2
+; CHECK-NEXT: and a7, t2, a7
+; CHECK-NEXT: sltu a2, a1, t0
+; CHECK-NEXT: and t2, t2, a6
+; CHECK-NEXT: mv a6, a2
+; CHECK-NEXT: beq a3, a7, .LBB53_10
+; CHECK-NEXT: # %bb.9:
+; CHECK-NEXT: sltu a6, a3, a7
+; CHECK-NEXT: .LBB53_10:
+; CHECK-NEXT: sub t3, a5, t2
+; CHECK-NEXT: sltu a5, a5, t2
+; CHECK-NEXT: sub a4, a4, t1
+; CHECK-NEXT: sub a3, a3, a7
+; CHECK-NEXT: sub a1, a1, t0
+; CHECK-NEXT: sltu a7, t3, a6
+; CHECK-NEXT: sub a4, a4, a5
+; CHECK-NEXT: sub a5, t3, a6
+; CHECK-NEXT: sub a3, a3, a2
+; CHECK-NEXT: sub a2, a4, a7
+; CHECK-NEXT: sw a1, 0(a0)
+; CHECK-NEXT: sw a3, 4(a0)
+; CHECK-NEXT: sw a5, 8(a0)
+; CHECK-NEXT: sw a2, 12(a0)
+; CHECK-NEXT: ret
+ %cmp = icmp ult i128 %x, %y
+ %select = select i1 %cmp, i128 0, i128 %y
+ %sub = sub nuw i128 %x, %select
+ ret i128 %sub
+}
+
+define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a2, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: sll a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %shl = shl i32 %sub, %select
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a2, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a2, a2, a1
+; CHECK-NEXT: sub a2, a0, a2
+; CHECK-NEXT: bltu a0, a1, .LBB55_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: li a0, 4
+; CHECK-NEXT: sll a0, a2, a0
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB55_2:
+; CHECK-NEXT: li a0, 2
+; CHECK-NEXT: sll a0, a2, a0
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %select2 = select i1 %cmp, i32 2, i32 4
+ %shl = shl i32 %sub, %select2
+ ret i32 %shl
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index d67db77c04a8e..844f6796f10b6 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64I
+; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RV64ZBB
+; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBB
declare i32 @llvm.ctlz.i32(i32, i1)
@@ -1562,17 +1562,11 @@ define i64 @orc_b_i64(i64 %a) {
}
define i64 @srai_slli(i16 signext %0) {
-; RV64I-LABEL: srai_slli:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 57
-; RV64I-NEXT: srai a0, a0, 63
-; RV64I-NEXT: ret
-;
-; RV64ZBB-LABEL: srai_slli:
-; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: slli a0, a0, 57
-; RV64ZBB-NEXT: srai a0, a0, 63
-; RV64ZBB-NEXT: ret
+; CHECK-LABEL: srai_slli:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 57
+; CHECK-NEXT: srai a0, a0, 63
+; CHECK-NEXT: ret
%2 = shl i16 %0, 9
%sext = ashr i16 %2, 15
%3 = sext i16 %sext to i64
@@ -1580,17 +1574,11 @@ define i64 @srai_slli(i16 signext %0) {
}
define i64 @srai_slli2(i16 signext %0) {
-; RV64I-LABEL: srai_slli2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: slli a0, a0, 57
-; RV64I-NEXT: srai a0, a0, 62
-; RV64I-NEXT: ret
-;
-; RV64ZBB-LABEL: srai_slli2:
-; RV64ZBB: # %bb.0:
-; RV64ZBB-NEXT: slli a0, a0, 57
-; RV64ZBB-NEXT: srai a0, a0, 62
-; RV64ZBB-NEXT: ret
+; CHECK-LABEL: srai_slli2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: slli a0, a0, 57
+; CHECK-NEXT: srai a0, a0, 62
+; CHECK-NEXT: ret
%2 = shl i16 %0, 9
%sext = ashr i16 %2, 14
%3 = sext i16 %sext to i64
@@ -1598,19 +1586,12 @@ define i64 @srai_slli2(i16 signext %0) {
}
define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 {
-; RV64I-LABEL: func0000000000000001:
-; RV64I: # %bb.0: # %entry
-; RV64I-NEXT: slli a1, a1, 59
-; RV64I-NEXT: srai a1, a1, 63
-; RV64I-NEXT: addw a0, a1, a0
-; RV64I-NEXT: ret
-;
-; RV64ZBB-LABEL: func0000000000000001:
-; RV64ZBB: # %bb.0: # %entry
-; RV64ZBB-NEXT: slli a1, a1, 59
-; RV64ZBB-NEXT: srai a1, a1, 63
-; RV64ZBB-NEXT: addw a0, a1, a0
-; RV64ZBB-NEXT: ret
+; CHECK-LABEL: func0000000000000001:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: slli a1, a1, 59
+; CHECK-NEXT: srai a1, a1, 63
+; CHECK-NEXT: addw a0, a1, a0
+; CHECK-NEXT: ret
entry:
%2 = shl i8 %1, 3
%3 = ashr i8 %2, 7
@@ -1699,3 +1680,145 @@ entry:
%cmp = icmp eq i32 %popcnt, 1
ret i1 %cmp
}
+
+define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: sub_if_uge_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: zext.b a2, a1
+; CHECK-NEXT: zext.b a3, a0
+; CHECK-NEXT: sltu a2, a3, a2
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i8 %x, %y
+ %select = select i1 %cmp, i8 0, i8 %y
+ %sub = sub nuw i8 %x, %select
+ ret i8 %sub
+}
+
+define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
+; RV64I-LABEL: sub_if_uge_i16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a2, 16
+; RV64I-NEXT: addiw a2, a2, -1
+; RV64I-NEXT: and a3, a1, a2
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: sltu a2, a2, a3
+; RV64I-NEXT: addi a2, a2, -1
+; RV64I-NEXT: and a1, a2, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBB-LABEL: sub_if_uge_i16:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: zext.h a2, a1
+; RV64ZBB-NEXT: zext.h a3, a0
+; RV64ZBB-NEXT: sltu a2, a3, a2
+; RV64ZBB-NEXT: addi a2, a2, -1
+; RV64ZBB-NEXT: and a1, a2, a1
+; RV64ZBB-NEXT: sub a0, a0, a1
+; RV64ZBB-NEXT: ret
+ %cmp = icmp ult i16 %x, %y
+ %select = select i1 %cmp, i16 0, i16 %y
+ %sub = sub nuw i16 %x, %select
+ ret i16 %sub
+}
+
+define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: sltu a2, a3, a2
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ ret i32 %sub
+}
+
+define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: sub_if_uge_i64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sltu a2, a0, a1
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: sub a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i64 %x, %y
+ %select = select i1 %cmp, i64 0, i64 %y
+ %sub = sub nuw i64 %x, %select
+ ret i64 %sub
+}
+
+define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
+; CHECK-LABEL: sub_if_uge_i128:
+; CHECK: # %bb.0:
+; CHECK-NEXT: beq a1, a3, .LBB66_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sltu a4, a1, a3
+; CHECK-NEXT: j .LBB66_3
+; CHECK-NEXT: .LBB66_2:
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: .LBB66_3:
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a3, a4, a3
+; CHECK-NEXT: and a2, a4, a2
+; CHECK-NEXT: sltu a4, a0, a2
+; CHECK-NEXT: sub a1, a1, a3
+; CHECK-NEXT: sub a1, a1, a4
+; CHECK-NEXT: sub a0, a0, a2
+; CHECK-NEXT: ret
+ %cmp = icmp ult i128 %x, %y
+ %select = select i1 %cmp, i128 0, i128 %y
+ %sub = sub nuw i128 %x, %select
+ ret i128 %sub
+}
+
+define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: sltu a2, a3, a2
+; CHECK-NEXT: addi a2, a2, -1
+; CHECK-NEXT: and a1, a2, a1
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %shl = shl i32 %sub, %select
+ ret i32 %shl
+}
+
+define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sext.w a2, a1
+; CHECK-NEXT: sext.w a3, a0
+; CHECK-NEXT: sltu a4, a3, a2
+; CHECK-NEXT: addi a4, a4, -1
+; CHECK-NEXT: and a1, a4, a1
+; CHECK-NEXT: subw a0, a0, a1
+; CHECK-NEXT: bltu a3, a2, .LBB68_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: li a1, 4
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB68_2:
+; CHECK-NEXT: li a1, 2
+; CHECK-NEXT: sllw a0, a0, a1
+; CHECK-NEXT: ret
+ %cmp = icmp ult i32 %x, %y
+ %select = select i1 %cmp, i32 0, i32 %y
+ %sub = sub nuw i32 %x, %select
+ %select2 = select i1 %cmp, i32 2, i32 4
+ %shl = shl i32 %sub, %select2
+ ret i32 %shl
+}
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