[llvm] [AArch64][GlobalISel] Fix lowering of i64->f32 itofp. (PR #132703)

[David Green via llvm-commits]

================
@@ -7609,6 +7609,22 @@ LegalizerHelper::lowerU64ToF64BitFloatOps(MachineInstr &MI) {
   return Legalized;
 }
 
+/// i64->fp16 itofp can be lowered to i64->f64,f64->f32,f32->f16. We cannot
+/// convert fpround f64->f16 without double-rounding, so we manually perform the
+/// lowering here where we know it is valid.
+static LegalizerHelper::LegalizeResult
+loweri64tof16ITOFP(MachineInstr &MI, Register Dst, LLT DstTy, Register Src,
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davemgreen wrote:

AFAIR: We are trying to lower a `vNi64->vNf16 uitofp`, without scalarizing. For example a `v4i64->v4f16 uitofp` turns into
```
ucvtf v0.2d, v0.2d
ucvtf v1.2d, v1.2d
fcvtn v0.2s, v0.2d
fcvtn2 v0.4s, v1.2d
fcvtn v0.4h, v0.4s
```
So a `v4f16 fptrunc(v4f32 fptrunc(v4f64 uitofp(v4i64)))` (where the v4i64 is two vectors). If we initially say "widen type0 to f64" we get `v4f16 fptrunc(v4f64 uitofp(v4i64))` and the `v4f16 fptrunc(v4f64` needs to scalarize. If we say "widen type0 to f32" we get `v4f16 fptrunc(v4f32 uitofp(v4i64))` and the `v4f32 uitofp(v4i64` needs to scalarize (the point of this patch). That is what I meant by "there isn't a way to communicate two different types", you can't give it "widen to f64 via f32 please".

Note: for scalar we want it to become `f16 fptrunc(f64 uitofp(i64))` because we have an instruction for f64->f16 fptrunc. We don't want it to become two fptruncs.

(Whilst thinking about this, I wondered if we could lower to `uqxtn+uqxtn2+scvtf+fcvtn` for fp16 instead, but that would involve a TRUNCATE_USAT_U that we don't have for globalisel yet).

Currently we have it that lower means legalize via two steps, widen means lower directly, which might not be the best but fits into "lower does something different". What was the concrete suggestion for how this should work?

https://github.com/llvm/llvm-project/pull/132703