[llvm] [AArch64] Make use of byte FPR stores for bytes extracted from vectors (PR #134117)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

I believe the decision to have a dedicated MVT for mfp8 means we can simplify things further because we don't need the truncating store (given that was my failed suggestion to remove the need for a dedicated MVT) and can instead have isel to store `aarch64mfp8` directly.  In doing this I believe we can unify the i8 support with the previous support for i16-i64 because at the end of the day the logic is essentially:
```
Move lane_to_store to lane_0
bitcast to a vector we can extract a subreg from
extract the subreg
store the subreg
```
Whilst the new MVT makes this slightly more awkward I think we're only really talking about having logic like:
```
EVT FPElemVT = ElemVT == MVT::i8 ? MVT::i8 : EVT::getFloatingPointVT(***);
EVT FPMemVT = MemVT == MVT::i8 ? MVT::aarch64mfp8 : EVT::getFloatingPointVT(***);
```
but beyond the VTs in play the resulting DAG will hopefully be the same across all the types.

https://github.com/llvm/llvm-project/pull/134117