[llvm] [AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128. (PR #134068)

[Paul Walker via llvm-commits]

================
@@ -2911,6 +2914,17 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
       return false;
   }
 
+  // Pairing SVE fills/spills is only valid for little-endian targets that
+  // implement VLS 128.
+  switch (MI.getOpcode()) {
+  default:
+    break;
+  case AArch64::LDR_ZXI:
+  case AArch64::STR_ZXI:
+    return Subtarget.isLittleEndian() &&
+           Subtarget.getSVEVectorSizeInBits() == 128;
----------------
paulwalker-arm wrote:

```suggestion
    if (!Subtarget.isLittleEndian() ||
        Subtarget.getSVEVectorSizeInBits() != 128)
      return false;
```
So that we continue to bail based on the later check plus if anything new is added.

https://github.com/llvm/llvm-project/pull/134068