[llvm] [LoongArch] Pre-commit test for vector byte rotate (PR #134839)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 8 03:57:38 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-loongarch
Author: None (tangaac)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/134839.diff
2 Files Affected:
- (added) llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-rotate.ll (+143)
- (added) llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-rotate.ll (+142)
``````````diff
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-rotate.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-rotate.ll
new file mode 100644
index 0000000000000..88d9037e3a9e9
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-rotate.ll
@@ -0,0 +1,143 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+
+;; TODO For these special shuffle mask, we can lower it to xvbsll + xvbsrl + xvor.
+
+define <32 x i8> @byte_rotate_v32_i8_1(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: byte_rotate_v32_i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48>
+ ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @byte_rotate_v32_i8_2(<32 x i8> %a, <32 x i8> %b) {
+; CHECK-LABEL: byte_rotate_v32_i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT: xvshuf.b $xr0, $xr1, $xr0, $xr2
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 45, i32 46, i32 47, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 61, i32 62, i32 63, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28>
+ ret <32 x i8> %shuffle
+}
+
+define <32 x i8> @byte_rotate_v32_i8_3(<32 x i8> %a) {
+; CHECK-LABEL: byte_rotate_v32_i8_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT: xvshuf.b $xr0, $xr0, $xr0, $xr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 16>
+ ret <32 x i8> %shuffle
+}
+
+
+define <16 x i16> @byte_rotate_v16i16_1(<16 x i16> %a, <16 x i16> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v16i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 11, i32 12, i32 13, i32 14, i32 15, i32 24, i32 25, i32 26>
+ ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @byte_rotate_v16i16_2(<16 x i16> %a, <16 x i16> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v16i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: xvshuf.h $xr2, $xr1, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 21, i32 22, i32 23, i32 0, i32 1, i32 2,i32 3, i32 4, i32 29, i32 30, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12>
+ ret <16 x i16> %shuffle
+}
+
+define <16 x i16> @byte_rotate_v16i16_3(<16 x i16> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v16i16_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: xvshuf.h $xr1, $xr0, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10>
+ ret <16 x i16> %shuffle
+}
+
+define <8 x i32> @byte_rotate_v8i32_1(<8 x i32> %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v8i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
+ ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @byte_rotate_v8i32_2(<8 x i32> %a, <8 x i32> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v8i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT: xvshuf.w $xr2, $xr1, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 11, i32 0, i32 1, i32 2, i32 15, i32 4, i32 5, i32 6>
+ ret <8 x i32> %shuffle
+}
+
+define <8 x i32> @byte_rotate_v8i32_3(<8 x i32> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v8i32_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xvshuf4i.w $xr0, $xr0, 57
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
+ ret <8 x i32> %shuffle
+}
+
+define <4 x i64> @byte_rotate_v4i64_1(<4 x i64> %a, <4 x i64> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 4, i32 3, i32 6>
+ ret <4 x i64> %shuffle
+}
+
+define <4 x i64> @byte_rotate_v4i64_2(<4 x i64> %a, <4 x i64> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT: xvld $xr2, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT: xvshuf.d $xr2, $xr1, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 5, i32 0, i32 7, i32 2>
+ ret <4 x i64> %shuffle
+}
+
+define <4 x i64> @byte_rotate_v4i64_3(<4 x i64> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v4i64_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT: xvld $xr1, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT: xvshuf.d $xr1, $xr0, $xr0
+; CHECK-NEXT: xvori.b $xr0, $xr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+ ret <4 x i64> %shuffle
+}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-rotate.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-rotate.ll
new file mode 100644
index 0000000000000..eb92d236f43a0
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-byte-rotate.ll
@@ -0,0 +1,142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+;; TODO For these special shuffle mask, we can lower it to vbsll + vbsrl + vor.
+
+define <16 x i8> @byte_rotate_v16i8_1(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v16i8_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI0_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI0_0)
+; CHECK-NEXT: vshuf.b $vr0, $vr1, $vr0, $vr2
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @byte_rotate_v16i8_2(<16 x i8> %a, <16 x i8> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v16i8_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI1_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI1_0)
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @byte_rotate_v16i8_3(<16 x i8> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v16i8_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI2_0)
+; CHECK-NEXT: vshuf.b $vr0, $vr0, $vr0, $vr1
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <16 x i8> %a, <16 x i8> poison, <16 x i32> <i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <16 x i8> %shuffle
+}
+
+define <8 x i16> @byte_rotate_v8i16_1(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v8i16_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI3_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI3_0)
+; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @byte_rotate_v8i16_2(<8 x i16> %a, <8 x i16> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v8i16_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
+; CHECK-NEXT: vshuf.h $vr2, $vr1, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
+ ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @byte_rotate_v8i16_3(<8 x i16> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v8i16_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI5_0)
+; CHECK-NEXT: vshuf.h $vr1, $vr0, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <8 x i16> %a, <8 x i16> poison, <8 x i32> <i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4>
+ ret <8 x i16> %shuffle
+}
+
+define <4 x i32> @byte_rotate_v4i32_1(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v4i32_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI6_0)
+; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @byte_rotate_v4i32_2(<4 x i32> %a, <4 x i32> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v4i32_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI7_0)
+; CHECK-NEXT: vshuf.w $vr2, $vr1, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+ ret <4 x i32> %shuffle
+}
+
+define <4 x i32> @byte_rotate_v4i32_3(<4 x i32> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v4i32_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vshuf4i.w $vr0, $vr0, 147
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
+ ret <4 x i32> %shuffle
+}
+
+define <2 x i64> @byte_rotate_v2i64_1(<2 x i64> %a, <2 x i64> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI9_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI9_0)
+; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
+ ret <2 x i64> %shuffle
+}
+
+define <2 x i64> @byte_rotate_v2i64_2(<2 x i64> %a, <2 x i64> %b) nounwind {
+; CHECK-LABEL: byte_rotate_v2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI10_0)
+; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI10_0)
+; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr2, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
+ ret <2 x i64> %shuffle
+}
+
+define <2 x i64> @byte_rotate_v2i64_3(<2 x i64> %a) nounwind {
+; CHECK-LABEL: byte_rotate_v2i64_3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI11_0)
+; CHECK-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI11_0)
+; CHECK-NEXT: vshuf.d $vr1, $vr0, $vr0
+; CHECK-NEXT: vori.b $vr0, $vr1, 0
+; CHECK-NEXT: ret
+ %shuffle = shufflevector <2 x i64> %a, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x i64> %shuffle
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/134839
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