[llvm] [AMDGPU] Fix undefined scc register in successor block of SI_KILL terminators (PR #134718)

[Juan Manuel Martinez Caamaño via llvm-commits]

================
@@ -4516,6 +4516,38 @@ SITargetLowering::splitKillBlock(MachineInstr &MI,
   MachineBasicBlock *SplitBB = BB->splitAt(MI, false /*UpdateLiveIns*/);
   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
   MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
+
+  // Check if SCC register is used in the successor block
+  bool IsSCCUsedInSuccessor = false;
+  for (const MachineInstr &SuccMI : *SplitBB) {
+    // Check for uses of SCC in the instruction's operands
+    for (const MachineOperand &MO : SuccMI.operands()) {
+      if (MO.isReg() && MO.getReg() == AMDGPU::SCC && !MO.isDef()) {
+        IsSCCUsedInSuccessor = true;
+        break;
+      }
+    }
+
+    // Also check for implicit uses of SCC
+    if(!IsSCCUsedInSuccessor){
+      const MCInstrDesc &Desc = SuccMI.getDesc();
+      if (Desc.hasImplicitUseOfPhysReg(AMDGPU::SCC)) {
+        IsSCCUsedInSuccessor = true;
+        break;
+      }
+    }
+    
+    if (IsSCCUsedInSuccessor)
+      break;
+  }
----------------
jmmartinez wrote:

If you move this code to a helper function we would end up with less awkward branching:

```cpp
for (const MachineInstr &SuccMI : *SplitBB) {
    // Check for uses of SCC in the instruction's operands
    for (const MachineOperand &MO : SuccMI.operands())
      if (MO.isReg() && MO.getReg() == AMDGPU::SCC && !MO.isDef())
        return true;

    // Also check for implicit uses of SCC
    const MCInstrDesc &Desc = SuccMI.getDesc();
    if (Desc.hasImplicitUseOfPhysReg(AMDGPU::SCC))
      return true;
}
```

https://github.com/llvm/llvm-project/pull/134718