[llvm] [LLVM][CodeGen][SVE] Improve lowering of fixed length masked mem ops. (PR #134402)

[Paul Walker via llvm-commits]

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@@ -20190,6 +20190,12 @@ performInsertSubvectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   EVT VecVT = Vec.getValueType();
   EVT SubVT = SubVec.getValueType();
 
+  // Promote fixed length vector zeros.
+  if (VecVT.isScalableVector() && SubVT.isFixedLengthVector() &&
+      Vec.isUndef() && isZerosVector(SubVec.getNode()))
+    return VecVT.isInteger() ? DAG.getConstant(0, DL, VecVT)
+                             : DAG.getConstantFP(0, DL, VecVT);
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paulwalker-arm wrote:

> Not sure in practice if we'll actually end up with different assembly or not?

We will because NEON only has reg-reg and reg-zero compare instructions whereas SVE has reg-imm as well.  You can see this today by changing the existing SVE VLS tests to use non-zero immediates where the generated code emits an unnecessary splat.


https://github.com/llvm/llvm-project/pull/134402