[llvm] [AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (PR #133242)

[Sebastian Neubauer via llvm-commits]

Flakebi wrote:

I created some small tests, to make sure this works as intended in all cases. Probably makes sense to add them here.
One of them yields surprising results, probably something that should be fixed.

PAL tests:
```llvm
; RUN: llc -mcpu=gfx1200 -o - < %s | FileCheck %s
; Check that reads of a VGPR in kernels counts towards VGPR count, but in functions, only writes of VGPRs count towards VGPR count.
target triple = "amdgcn--amdpal"

@global = addrspace(1) global i32 poison, align 4

; CHECK-LABEL: amdpal.pipelines:

; Neither uses not writes a VGPR, but the hardware initializes the VGPRs that the kernel receives, so they count as used.
; CHECK-LABEL: .entry_point_symbol: kernel_use
; CHECK: .vgpr_count:     0x20
define amdgpu_cs void @kernel_use([32 x i32] %args) {
entry:
  %a = extractvalue [32 x i32] %args, 14
  store i32 %a, ptr addrspace(1) @global
  ret void
}

; Neither uses not writes a VGPR
; CHECK-LABEL: gfx_func:
; CHECK: .vgpr_count:     0x20
define amdgpu_gfx [32 x i32] @gfx_func([32 x i32] %args) {
entry:
  ret [32 x i32] %args
}

; Neither uses not writes a VGPR
; CHECK-LABEL: chain_func:
; CHECK: .vgpr_count:     0x1
define amdgpu_cs_chain void @chain_func([32 x i32] %args) {
entry:
  call void (ptr, i32, {}, [32 x i32], i32, ...) @llvm.amdgcn.cs.chain.p0.i32.s.a(
        ptr @chain_func, i32 0, {} inreg {}, [32 x i32] %args, i32 0)
  unreachable
}
```

The (to me) surprising one is `gfx_func`, it only contains SALU instructions, so should have no defs of VGPRs and only uses for the return. I would expect it to have `vgpr_count: 0x0` or maybe 0x1.

This one works as expected:
```llvm
; RUN: llc -mcpu=gfx1200 -o - < %s | FileCheck %s
target triple = "amdgcn--amdpal"

declare amdgpu_gfx void @gfx_dummy([32 x i32] %args)

; CHECK-LABEL: .entry_point_symbol: kernel_call
; CHECK: .vgpr_count:     0x20
define amdgpu_cs void @kernel_call([32 x i32] %args) {
entry:
  call amdgpu_gfx void @gfx_dummy([32 x i32] %args)
  ret void
}
```

Carefully crafted compute test (the hw initializes at most one VGPR, so the test needs to ensure, no VGPR is ever written from any instruction). Also works as expected (correctly marks one VGPR as used).
```llvm
; RUN: llc -mcpu=gfx1200 -o - < %s | FileCheck %s
target triple = "amdgcn-amd-amdhsa"

@global = addrspace(1) global i32 poison, align 4

; Carefully crafted kernel that uses v0 but never writes a VGPR or reads another VGPR.
; Only hardware-initialized VGPRs (v0) are read in this kernel.

; CHECK-LABEL: amdhsa.kernels:
; CHECK: .vgpr_count:     1
define amdgpu_kernel void @kernel(ptr addrspace(8) %rsrc) #0 {
entry:
  %id = call i32 @llvm.amdgcn.workitem.id.x()
  call void @llvm.amdgcn.raw.ptr.buffer.store.i32(i32 %id, ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
  ret void
}

attributes #0 = { "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
```

https://github.com/llvm/llvm-project/pull/133242