[llvm] 6fb6741 - [RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-03-30T22:38:26-07:00
New Revision: 6fb674174ecc1d27b0d303c89c666d949f7afee5

URL: https://github.com/llvm/llvm-project/commit/6fb674174ecc1d27b0d303c89c666d949f7afee5
DIFF: https://github.com/llvm/llvm-project/commit/6fb674174ecc1d27b0d303c89c666d949f7afee5.diff

LOG: [RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC

Due to a copy paste mistake we used simm12 instead of the correct
type. This doesn't matter in practice because we only generate these
instructions with C++ code and we expand them before the AsmPrinter.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
index 16cc0e5a61f0b..32f533b8f1146 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
@@ -98,17 +98,17 @@ def PseudoCCADDI : Pseudo<(outs GPR:$dst),
                           ReadSFBALU]>;
 def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
                           (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
-                           GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+                           GPR:$falsev, GPR:$rs1, uimmlog2xlen:$shamt), []>,
                    Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
                           ReadSFBALU]>;
 def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
                           (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
-                           GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+                           GPR:$falsev, GPR:$rs1, uimmlog2xlen:$shamt), []>,
                    Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
                           ReadSFBALU]>;
 def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
                           (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
-                           GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+                           GPR:$falsev, GPR:$rs1, uimmlog2xlen:$shamt), []>,
                    Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
                           ReadSFBALU]>;
 def PseudoCCANDI : Pseudo<(outs GPR:$dst),
@@ -161,17 +161,17 @@ def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
                            ReadSFBALU]>;
 def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
                            (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
-                            GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+                            GPR:$falsev, GPR:$rs1, uimm5:$shamt), []>,
                     Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
                            ReadSFBALU]>;
 def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
                            (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
-                            GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+                            GPR:$falsev, GPR:$rs1, uimm5:$shamt), []>,
                     Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
                            ReadSFBALU]>;
 def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
                            (ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
-                            GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+                            GPR:$falsev, GPR:$rs1, uimm5:$shamt), []>,
                     Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
                            ReadSFBALU]>;