[llvm] [MC] Simplify MCBinaryExpr printing by reducing parentheses for +/- (PR #133674)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 30 20:37:47 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-arm
Author: Fangrui Song (MaskRay)
<details>
<summary>Changes</summary>
The existing pretty printer generates excessive parentheses for MCBinaryExpr expressions with + or - operators. This update removes unnecessary parentheses around the two operands of such expressions. Since relocatable expressions only use + and -, this change improves readability in most cases.
Examples:
- (SymA - SymB) + C now prints as SymA - SymB + C
- expr + (MCTargetExpr) now prints as expr + MCTargetExpr, with this change primarily affecting AMDGPUMCExpr.
---
Patch is 373.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/133674.diff
87 Files Affected:
- (modified) llvm/include/llvm/MC/MCExpr.h (+2-1)
- (modified) llvm/lib/MC/MCExpr.cpp (+31-20)
- (modified) llvm/test/CodeGen/AMDGPU/agpr-register-count.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/function-resource-usage.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/mcexpr-knownbits-assign-crash-gh-issue-110930.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/recursion.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/recursive-resource-usage-mcexpr.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/unnamed-function-resource-info.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/arm-isel-globals-pic.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/GlobalISel/thumb-isel-globals-pic.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/elf-preemption.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/globals.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/litpool-licm.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/load-global.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/load-global2.ll (+1-1)
- (modified) llvm/test/CodeGen/ARM/plt-relative-reloc.ll (+3-3)
- (modified) llvm/test/CodeGen/ARM/stack-guard-elf.ll (+10-10)
- (modified) llvm/test/CodeGen/ARM/stack-guard-rwpi.ll (+1-1)
- (modified) llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-largeaccess.ll (+24-24)
- (modified) llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll (+16-16)
- (modified) llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll (+4-4)
- (modified) llvm/test/CodeGen/PowerPC/aix-small-tls-globalvarattr-funcattr.ll (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-small-tls-globalvarattr-targetattr.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/dso_local_equivalent.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/plt-relative-reloc.ll (+2-2)
- (modified) llvm/test/CodeGen/Thumb2/tpsoft.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/abi-isel.ll (+48-48)
- (modified) llvm/test/CodeGen/X86/atomic-minmax-i6432.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/inline-asm-i-constraint-i1.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/relptr-rodata.ll (+1-1)
- (modified) llvm/test/CodeGen/X86/wineh-coreclr.ll (+42-42)
- (modified) llvm/test/CodeGen/X86/x86-64-plt-relative-reloc.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/x86-plt-relative-reloc.ll (+3-3)
- (modified) llvm/test/MC/AArch64/elf-reloc-ptrauth.s (+6-6)
- (modified) llvm/test/MC/AMDGPU/expressions.s (+2-2)
- (modified) llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx10.s (+23-23)
- (modified) llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx11.s (+23-23)
- (modified) llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx12.s (+22-22)
- (modified) llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx7.s (+17-17)
- (modified) llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx8.s (+17-17)
- (modified) llvm/test/MC/AMDGPU/hsa-sym-exprs-gfx90a.s (+19-19)
- (modified) llvm/test/MC/AMDGPU/mcexpr_amd.s (+2-2)
- (modified) llvm/test/MC/ARM/basic-arm-instructions.s (+2-2)
- (modified) llvm/test/MC/ARM/elf-movt.s (+2-2)
- (modified) llvm/test/MC/ARM/macho-word-reloc-thumb.s (+1-1)
- (modified) llvm/test/MC/AVR/inst-brbc.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brbs.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brcc.s (+6-6)
- (modified) llvm/test/MC/AVR/inst-brcs.s (+6-6)
- (modified) llvm/test/MC/AVR/inst-breq.s (+6-6)
- (modified) llvm/test/MC/AVR/inst-brge.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brhc.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brhs.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brid.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brie.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brlo.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brlt.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brmi.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brne.s (+6-6)
- (modified) llvm/test/MC/AVR/inst-brpl.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brsh.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brtc.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brts.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brvc.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-brvs.s (+4-4)
- (modified) llvm/test/MC/AVR/inst-rcall.s (+8-8)
- (modified) llvm/test/MC/AVR/inst-rjmp.s (+14-14)
- (modified) llvm/test/MC/AsmParser/directive_fill.s (+1-1)
- (modified) llvm/test/MC/AsmParser/expr_symbol_modifiers.s (+1-1)
- (modified) llvm/test/MC/COFF/cross-section-relative.ll (+3-3)
- (modified) llvm/test/MC/ELF/reloc-directive.s (+2-2)
- (modified) llvm/test/MC/Lanai/memory.s (+2-2)
- (modified) llvm/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll (+2-2)
- (modified) llvm/test/MC/Mips/expr1.s (+8-8)
- (modified) llvm/test/MC/Mips/memory-offsets.s (+4-4)
- (modified) llvm/test/MC/PowerPC/ppc32-tls.s (+1-1)
- (modified) llvm/test/MC/RISCV/rvi-pseudos.s (+1-1)
- (modified) llvm/test/MC/SystemZ/insn-good-z196.s (+5-5)
- (modified) llvm/test/MC/SystemZ/insn-good-zEC12.s (+15-15)
- (modified) llvm/test/MC/SystemZ/insn-good.s (+410-410)
``````````diff
diff --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h
index d6829f2bcc734..12830ee648ae0 100644
--- a/llvm/include/llvm/MC/MCExpr.h
+++ b/llvm/include/llvm/MC/MCExpr.h
@@ -81,7 +81,8 @@ class MCExpr {
/// \name Utility Methods
/// @{
- void print(raw_ostream &OS, const MCAsmInfo *MAI) const;
+ void print(raw_ostream &OS, const MCAsmInfo *MAI,
+ int SurroundingPrec = 0) const;
void dump() const;
/// Returns whether the given symbol is used anywhere in the expression or
diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp
index 253247561354b..fa5c3dab1f115 100644
--- a/llvm/lib/MC/MCExpr.cpp
+++ b/llvm/lib/MC/MCExpr.cpp
@@ -37,10 +37,22 @@ STATISTIC(MCExprEvaluate, "Number of MCExpr evaluations");
} // end namespace stats
} // end anonymous namespace
+static int getPrecedence(MCBinaryExpr::Opcode Op) {
+ switch (Op) {
+ case MCBinaryExpr::Add:
+ case MCBinaryExpr::Sub:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
// VariantKind printing and formatting utilize MAI. operator<< (dump and some
// target code) specifies MAI as nullptr and should be avoided when MAI is
// needed.
-void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
+void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI,
+ int SurroundingPrec) const {
+ constexpr int MaxPrec = 9;
switch (getKind()) {
case MCExpr::Target:
return cast<MCTargetExpr>(this)->printImpl(OS, MAI);
@@ -98,24 +110,26 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
case MCUnaryExpr::Not: OS << '~'; break;
case MCUnaryExpr::Plus: OS << '+'; break;
}
- bool Binary = UE.getSubExpr()->getKind() == MCExpr::Binary;
- if (Binary) OS << "(";
- UE.getSubExpr()->print(OS, MAI);
- if (Binary) OS << ")";
+ UE.getSubExpr()->print(OS, MAI, MaxPrec);
return;
}
case MCExpr::Binary: {
const MCBinaryExpr &BE = cast<MCBinaryExpr>(*this);
-
- // Only print parens around the LHS if it is non-trivial.
- if (isa<MCConstantExpr>(BE.getLHS()) || isa<MCSymbolRefExpr>(BE.getLHS())) {
- BE.getLHS()->print(OS, MAI);
- } else {
+ // We want to avoid redundant parentheses for relocatable expressions like
+ // a-b+c.
+ //
+ // Print '(' if the current operator has lower precedence than the
+ // surrounding operator, or if the surrounding operator's precedence is
+ // unknown (set to HighPrecedence).
+ int Prec = getPrecedence(BE.getOpcode());
+ bool Paren = Prec < SurroundingPrec;
+ if (Paren)
OS << '(';
- BE.getLHS()->print(OS, MAI);
- OS << ')';
- }
+ // Many operators' precedence is different from C. Set the precedence to
+ // HighPrecedence for unknown operators.
+ int SubPrec = Prec ? Prec : MaxPrec;
+ BE.getLHS()->print(OS, MAI, SubPrec);
switch (BE.getOpcode()) {
case MCBinaryExpr::Add:
@@ -123,6 +137,8 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
if (const MCConstantExpr *RHSC = dyn_cast<MCConstantExpr>(BE.getRHS())) {
if (RHSC->getValue() < 0) {
OS << RHSC->getValue();
+ if (Paren)
+ OS << ')';
return;
}
}
@@ -150,14 +166,9 @@ void MCExpr::print(raw_ostream &OS, const MCAsmInfo *MAI) const {
case MCBinaryExpr::Xor: OS << '^'; break;
}
- // Only print parens around the LHS if it is non-trivial.
- if (isa<MCConstantExpr>(BE.getRHS()) || isa<MCSymbolRefExpr>(BE.getRHS())) {
- BE.getRHS()->print(OS, MAI);
- } else {
- OS << '(';
- BE.getRHS()->print(OS, MAI);
+ BE.getRHS()->print(OS, MAI, SubPrec + 1);
+ if (Paren)
OS << ')';
- }
return;
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
index 0e16ea10c019a..c7a20055a70d4 100644
--- a/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
+++ b/llvm/test/CodeGen/AMDGPU/agpr-register-count.ll
@@ -155,19 +155,19 @@ declare void @undef_func()
; GCN-LABEL: {{^}}kernel_call_undef_func:
; GCN: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0)
-; GFX90A: .amdhsa_accum_offset ((((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4))/4)-1)&(~65536))&63)+1)*4
+; GFX90A: .amdhsa_accum_offset (((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63)+1)*4
; GCN: .set kernel_call_undef_func.num_vgpr, max(32, amdgpu.max_num_vgpr)
; GCN: .set kernel_call_undef_func.num_agpr, max(0, amdgpu.max_num_agpr)
; GCN: NumVgprs: kernel_call_undef_func.num_vgpr
; GCN: NumAgprs: kernel_call_undef_func.num_agpr
; GCN: TotalNumVgprs: totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr)
-; GFX908: VGPRBlocks: ((alignto(max(max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0), 1), 4))/4)-1
-; GFX90A: VGPRBlocks: ((alignto(max(max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0), 1), 8))/8)-1
+; GFX908: VGPRBlocks: (alignto(max(max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0), 1), 4)/4)-1
+; GFX90A: VGPRBlocks: (alignto(max(max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0), 1), 8)/8)-1
; GCN: NumVGPRsForWavesPerEU: max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0)
-; GFX90A: AccumOffset: ((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4))/4)-1)+1)*4
-; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(kernel_call_undef_func.numbered_sgpr+(extrasgprs(kernel_call_undef_func.uses_vcc, kernel_call_undef_func.uses_flat_scratch, 1)), 1, 0), max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0))
-; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(kernel_call_undef_func.numbered_sgpr+(extrasgprs(kernel_call_undef_func.uses_vcc, kernel_call_undef_func.uses_flat_scratch, 1)), 1, 0), max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0))
-; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: ((((alignto(max(1, kernel_call_undef_func.num_vgpr), 4))/4)-1)&(~65536))&63
+; GFX90A: AccumOffset: ((alignto(max(1, kernel_call_undef_func.num_vgpr), 4)/4)-1+1)*4
+; GFX908: Occupancy: occupancy(10, 4, 256, 8, 10, max(kernel_call_undef_func.numbered_sgpr+extrasgprs(kernel_call_undef_func.uses_vcc, kernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0))
+; GFX90A: Occupancy: occupancy(8, 8, 512, 8, 8, max(kernel_call_undef_func.numbered_sgpr+extrasgprs(kernel_call_undef_func.uses_vcc, kernel_call_undef_func.uses_flat_scratch, 1), 1, 0), max(totalnumvgprs(kernel_call_undef_func.num_agpr, kernel_call_undef_func.num_vgpr), 1, 0))
+; GFX90A: COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: (((alignto(max(1, kernel_call_undef_func.num_vgpr), 4)/4)-1)&~65536)&63
define amdgpu_kernel void @kernel_call_undef_func() #0 {
bb:
call void @undef_func()
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
index 1d49e005234e3..9de6aea9385df 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
@@ -9,8 +9,8 @@
; ALL-LABEL: {{^}}kernel:
; ALL: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel.num_agpr, kernel.num_vgpr), 1, 0)
-; ALL-NEXT: .amdhsa_next_free_sgpr (max(kernel.numbered_sgpr+(extrasgprs(kernel.uses_vcc, kernel.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel.uses_vcc, kernel.uses_flat_scratch, 1))
-; GFX90A-NEXT: .amdhsa_accum_offset ((((((alignto(max(1, kernel.num_vgpr), 4))/4)-1)&(~65536))&63)+1)*4
+; ALL-NEXT: .amdhsa_next_free_sgpr max(kernel.numbered_sgpr+extrasgprs(kernel.uses_vcc, kernel.uses_flat_scratch, 1), 1, 0)-extrasgprs(kernel.uses_vcc, kernel.uses_flat_scratch, 1)
+; GFX90A-NEXT: .amdhsa_accum_offset (((((alignto(max(1, kernel.num_vgpr), 4)/4)-1)&~65536)&63)+1)*4
; ALL: .set kernel.num_vgpr, max(41, .Laliasee_default.num_vgpr)
; ALL-NEXT: .set kernel.num_agpr, max(0, .Laliasee_default.num_agpr)
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
index cbc8e7882c45e..fe27859eb0afd 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
@@ -10,7 +10,7 @@
; CHECK-LABEL: {{^}}kernel1:
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel1.num_agpr, kernel1.num_vgpr), 1, 0)
-; CHECK-NEXT: .amdhsa_next_free_sgpr (max(kernel1.numbered_sgpr+(extrasgprs(kernel1.uses_vcc, kernel1.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel1.uses_vcc, kernel1.uses_flat_scratch, 1))
+; CHECK-NEXT: .amdhsa_next_free_sgpr max(kernel1.numbered_sgpr+extrasgprs(kernel1.uses_vcc, kernel1.uses_flat_scratch, 1), 1, 0)-extrasgprs(kernel1.uses_vcc, kernel1.uses_flat_scratch, 1)
; CHECK: .set kernel1.num_vgpr, max(42, .Laliasee_vgpr32_sgpr76.num_vgpr)
; CHECK-NEXT: .set kernel1.num_agpr, max(0, .Laliasee_vgpr32_sgpr76.num_agpr)
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
index cdefbab93c62d..35b67351e85dd 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
@@ -8,7 +8,7 @@
; CHECK-LABEL: {{^}}kernel2:
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel2.num_agpr, kernel2.num_vgpr), 1, 0)
-; CHECK-NEXT: .amdhsa_next_free_sgpr (max(kernel2.numbered_sgpr+(extrasgprs(kernel2.uses_vcc, kernel2.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel2.uses_vcc, kernel2.uses_flat_scratch, 1))
+; CHECK-NEXT: .amdhsa_next_free_sgpr max(kernel2.numbered_sgpr+extrasgprs(kernel2.uses_vcc, kernel2.uses_flat_scratch, 1), 1, 0)-extrasgprs(kernel2.uses_vcc, kernel2.uses_flat_scratch, 1)
; CHECK: .set kernel2.num_vgpr, max(41, .Laliasee_vgpr64_sgpr102.num_vgpr)
; CHECK-NEXT: .set kernel2.num_agpr, max(0, .Laliasee_vgpr64_sgpr102.num_agpr)
diff --git a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
index 43dd0a7233604..3674d740b987b 100644
--- a/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
+++ b/llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
@@ -8,7 +8,7 @@
; CHECK-LABEL: {{^}}kernel3:
; CHECK: .amdhsa_next_free_vgpr max(totalnumvgprs(kernel3.num_agpr, kernel3.num_vgpr), 1, 0)
-; CHECK-NEXT: .amdhsa_next_free_sgpr (max(kernel3.numbered_sgpr+(extrasgprs(kernel3.uses_vcc, kernel3.uses_flat_scratch, 1)), 1, 0))-(extrasgprs(kernel3.uses_vcc, kernel3.uses_flat_scratch, 1))
+; CHECK-NEXT: .amdhsa_next_free_sgpr max(kernel3.numbered_sgpr+extrasgprs(kernel3.uses_vcc, kernel3.uses_flat_scratch, 1), 1, 0)-extrasgprs(kernel3.uses_vcc, kernel3.uses_flat_scratch, 1)
; CHECK: .set kernel3.num_vgpr, max(41, .Laliasee_vgpr256_sgpr102.num_vgpr)
; CHECK-NEXT: .set kernel3.num_agpr, max(0, .Laliasee_vgpr256_sgpr102.num_agpr)
diff --git a/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll b/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
index 512d58d3f996d..e152f2ddd5253 100644
--- a/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-resource-usage.ll
@@ -24,7 +24,7 @@ define void @use_vcc() #1 {
; GCN: .set indirect_use_vcc.num_vgpr, max(41, use_vcc.num_vgpr)
; GCN: .set indirect_use_vcc.num_agpr, max(0, use_vcc.num_agpr)
; GCN: .set indirect_use_vcc.numbered_sgpr, max(34, use_vcc.numbered_sgpr)
-; GCN: .set indirect_use_vcc.private_seg_size, 16+(max(use_vcc.private_seg_size))
+; GCN: .set indirect_use_vcc.private_seg_size, 16+max(use_vcc.private_seg_size)
; GCN: .set indirect_use_vcc.uses_vcc, or(1, use_vcc.uses_vcc)
; GCN: .set indirect_use_vcc.uses_flat_scratch, or(0, use_vcc.uses_flat_scratch)
; GCN: .set indirect_use_vcc.has_dyn_sized_stack, or(0, use_vcc.has_dyn_sized_stack)
@@ -42,7 +42,7 @@ define void @indirect_use_vcc() #1 {
; GCN: .set indirect_2level_use_vcc_kernel.num_vgpr, max(32, indirect_use_vcc.num_vgpr)
; GCN: .set indirect_2level_use_vcc_kernel.num_agpr, max(0, indirect_use_vcc.num_agpr)
; GCN: .set indirect_2level_use_vcc_kernel.numbered_sgpr, max(33, indirect_use_vcc.numbered_sgpr)
-; GCN: .set indirect_2level_use_vcc_kernel.private_seg_size, 0+(max(indirect_use_vcc.private_seg_size))
+; GCN: .set indirect_2level_use_vcc_kernel.private_seg_size, 0+max(indirect_use_vcc.private_seg_size)
; GCN: .set indirect_2level_use_vcc_kernel.uses_vcc, or(1, indirect_use_vcc.uses_vcc)
; GCN: .set indirect_2level_use_vcc_kernel.uses_flat_scratch, or(1, indirect_use_vcc.uses_flat_scratch)
; GCN: .set indirect_2level_use_vcc_kernel.has_dyn_sized_stack, or(0, indirect_use_vcc.has_dyn_sized_stack)
@@ -78,7 +78,7 @@ define void @use_flat_scratch() #1 {
; GCN: .set indirect_use_flat_scratch.num_vgpr, max(41, use_flat_scratch.num_vgpr)
; GCN: .set indirect_use_flat_scratch.num_agpr, max(0, use_flat_scratch.num_agpr)
; GCN: .set indirect_use_flat_scratch.numbered_sgpr, max(34, use_flat_scratch.numbered_sgpr)
-; GCN: .set indirect_use_flat_scratch.private_seg_size, 16+(max(use_flat_scratch.private_seg_size))
+; GCN: .set indirect_use_flat_scratch.private_seg_size, 16+max(use_flat_scratch.private_seg_size)
; GCN: .set indirect_use_flat_scratch.uses_vcc, or(1, use_flat_scratch.uses_vcc)
; GCN: .set indirect_use_flat_scratch.uses_flat_scratch, or(0, use_flat_scratch.uses_flat_scratch)
; GCN: .set indirect_use_flat_scratch.has_dyn_sized_stack, or(0, use_flat_scratch.has_dyn_sized_stack)
@@ -96,7 +96,7 @@ define void @indirect_use_flat_scratch() #1 {
; GCN: .set indirect_2level_use_flat_scratch_kernel.num_vgpr, max(32, indirect_use_flat_scratch.num_vgpr)
; GCN: .set indirect_2level_use_flat_scratch_kernel.num_agpr, max(0, indirect_use_flat_scratch.num_agpr)
; GCN: .set indirect_2level_use_flat_scratch_kernel.numbered_sgpr, max(33, indirect_use_flat_scratch.numbered_sgpr)
-; GCN: .set indirect_2level_use_flat_scratch_kernel.private_seg_size, 0+(max(indirect_use_flat_scratch.private_seg_size))
+; GCN: .set indirect_2level_use_flat_scratch_kernel.private_seg_size, 0+max(indirect_use_flat_scratch.private_seg_size)
; GCN: .set indirect_2level_use_flat_scratch_kernel.uses_vcc, or(1, indirect_use_flat_scratch.uses_vcc)
; GCN: .set indirect_2level_use_flat_scratch_kernel.uses_flat_scratch, or(1, indirect_use_flat_scratch.uses_flat_scratch)
; GCN: .set indirect_2level_use_flat_scratch_kernel.has_dyn_sized_stack, or(0, indirect_use_flat_scratch.has_dyn_sized_stack)
@@ -133,7 +133,7 @@ define void @use_10_vgpr() #1 {
; GCN: .set indirect_use_10_vgpr.num_vgpr, max(41, use_10_vgpr.num_vgpr)
; GCN: .set indirect_use_10_vgpr.num_agpr, max(0, use_10_vgpr.num_agpr)
; GCN: .set indirect_use_10_vgpr.numbered_sgpr, max(34, use_10_vgpr.numbered_sgpr)
-; GCN: .set indirect_use_10_vgpr.private_seg_size, 16+(max(use_10_vgpr.private_seg_size))
+; GCN: .set indirect_use_10_vgpr.private_seg_size, 16+max(use_10_vgpr.private_seg_size)
; GCN: .set indirect_use_10_vgpr.uses_vcc, or(1, use_10_vgpr.uses_vcc)
; GCN: .set indirect_use_10_vgpr.uses_flat_scratch, or(0, use_10_vgpr.uses_flat_scratch)
; GCN: .set indirect_use_10_vgpr.has_dyn_sized_stack, or(0, use_10_vgpr.has_dyn_sized_stack)
@@ -151,7 +151,7 @@ define void @indirect_use_10_vgpr() #0 {
; GCN: .set indirect_2_level_use_10_vgpr.num_vgpr, max(32, indirect_use_10_vgpr.num_vgpr)
; GCN: .set indirect_2_level_use_10_vgpr.num_agpr, max(0, indirect_use_10_vgpr.num_agpr)
; GCN: .set indirect_2_level_use_10_vgpr.numbered_sgpr, max(33, indirect_use_10_vgpr.numbered_sgpr)
-; GCN: .set indirect_2_level_use_10_vgpr.private_seg_size, 0+(max(indirect_use_10_vgpr.private_seg_size))
+; GCN: .set indirect_2_level_use_10_vgpr.private_seg_size, 0+max(indirect_use_10_vgpr.private_seg_size)
; GCN: .set indirect_2_level_use_10_vgpr.uses_vcc, or(1, indirect_use_10_vgpr.uses_vcc)
; GCN: .set indirect_2_level_use_10_vgpr.uses_flat_scratch, or(1, indirect_use_10_vgpr.uses_flat_scratch)
; GCN: .set indirect_2_level_use_10_vgpr.has_dyn_sized_stack, or(0, indirect_use_10_vgpr.has_dyn_sized_stack)
@@ -187,7 +187,7 @@ define void @use_50_vgpr() #1 {
; GCN: .set indirect_use_50_vgpr.num_vgpr, max(41, use_50_vgpr.num_vgpr)
; GCN: .set indirect_use_50_vgpr.num_agpr, max(0, use_50_vgpr.num_agpr)
; GCN: .set indirect_use_50_vgpr.numbered_sgpr, max(34, use_50_vgpr.numbered_sgpr)
-; GCN: .set indirect_use_50_vgpr.private_seg_size, 16+(max(use_50_vgpr.private_seg_size))
+; GCN: .set indirect_use_50_vgpr.private_seg_size, 16+max(use_50_vgpr.private_seg_size)
; GCN: .set indirect_use_50_vgpr.uses_vcc, or(1, use_50_vgpr.uses_vcc)
; GCN: .set indirect_use_50_vgpr.uses_flat_scratch, or(0, use_50_vgpr.uses_flat_scratch)
; GCN: .set indirect_use_50_vgpr.has_dyn_sized_stack, or(0, use_50_vgpr.has_dyn_sized_stack)
@@ -223,7 +223,7 @@ define void @use_80_sgpr() #1 {
; GCN: .set indirect_use_80_sgpr.num_vgpr, max(41, use_80_sgpr.num_vgpr)
; GCN: .set indirect_use_80_sgpr.num_agpr, max(0, use_80_sgpr.num_agpr)
; GCN: .set indirect_use_80_sgpr.numbered_sgpr, max(34, use_80_sgpr.numbered_sgpr)
-; GCN: .set indirect_use_80_sgpr.private_seg_size, 16+(max(use_80_sgpr.private_seg_size))
+; GCN: .set indirect_use_80_sgpr.private_seg_size, 16+max(use_80_sgpr.private_seg_size)
; GCN: .set indirect_use_80_sgpr.uses_vcc, or(1, use_80_sgpr.uses_vcc)
; GCN: .set indirect_use_80_sgpr.uses_flat_scratch, or(0, use_80_sgpr.uses_flat_scratch)
; GCN: .set indirect_use_80_sgpr.has_dyn_sized_stack, or(0, use_80_sgpr.has_dyn_sized_stack)
@@ -241,7 +241,7 @@ define void @indirect_use_80_sgpr() #1 {
; GCN: .set indirect_2_level_use_80_sgpr.num_vgpr, max(32, indirect_use_80_sgpr.num_vgpr)
; GCN: .set indirect_2_level_use_80_sgpr.num_agpr, max(0, indirect_use_80_sgpr.num_agpr)
; GCN: .set indirect_2_level_use_80_sgpr.numbered_sgpr, max(33, indirect_use_80_sgpr.numbered_sgpr)
-; GCN: .set indirect_2_level_use_80_sgpr.private_seg_size, 0+(max(indirect_use_80_sgpr.private_seg_size))
+; GCN: .set indirect_2_level_use_80_sgpr.private_seg_size, 0+max(indirect_use_80_sgpr.private_seg_size)
; GCN: .set indirect_2_level_use_80_sgpr.uses_vcc, or(1, indirect_use_80_sgpr.uses_vcc)
; GCN: .set indirect_2_level_use_80_sgpr.uses_flat_scratch, or(1, indirect_use_80_sgpr.uses_flat_scratch)
; GCN: .set indirect_2_level_use_80_sgpr.has_dyn_sized_stack, or(0, indirect_use_80_sgpr.has_dyn_sized_stack)
@@ -297,7 +297,7 @@ define void @use_stack1() #1 {
; GCN: .set indirect_use_stack.num_vgpr, max(41, use_stack0.num_vgpr)
; GCN: .set indirect_use_stack.num_agpr, max(0, use_stack0.num_agpr)
; GCN: .set indirect_use_stack.numbered_sgpr, max(34, use_stack0.numbered_sgpr)
-; GCN: .set indirect_use_stack.private_seg_size, 80+(max(use_stack0.private_seg_size))
+; GCN: .set indirect_use_stack.private_seg_size, 80+max(use_stack0.private_seg_size)
; GCN: .set indirect_use_stack.uses_vcc, or(1, use_stack0.uses_vcc)
; GCN: .set indirect_use_stack.uses_flat_scratch, or(0, use_stack0.uses_flat_scratch)
; GCN: .set indirect_use_stack.has_dyn_sized_stack, or(0, use_stack0.has_dyn_sized_stack)
@@ -317,7 +317,7 @@ define void @indirect_use_stack() #1 {
; GCN: .set indirect_2_level_use_stack.num_vgpr, max(32, indirect_use_stack.num_vgpr)
; GCN: .set indirect_2_level_use_stack.num_agpr, max(0, indirect_use_stack.num_agpr)
; GCN: .set indirect_2_level_use_stack.numbered_sgpr, max(33, indirect_use_stack.numbered_sgpr)
-; GCN: .set indirect_2_level_use_stack.private_seg_size, 0+(max(indirect_use_stack.private_seg_size))
+; GCN: .set indirect_2_level_use_stack.private_seg_size, 0+max(indirect_use_stack.private_seg_size)
; GCN: .set indirect_2_level_use_stack.uses_vcc, or(1, indirect_use_stack.uses_vcc)
; GCN: .set indirect_2_level_use_stack.uses_flat_scratch, or(1, indirect_use_stack.uses_flat_scratch)
; GCN: .set indirect_2_level_use_stack.has_dyn_sized_stack, or(0, indirect_use_stack.has_dyn_sized_stack)
@@ -337,7 +337,7 @@ define amdgpu_kernel void @indirect_2_level_use_stack() #0 {
; GCN: .set multi_call_use_use_stack.num_vgpr, max(41, use_stack0.num_vgpr, use_stack1.num_vgpr)
; GCN: .set multi_call_use_use_stack.num_agpr, max...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/133674
More information about the llvm-commits
mailing list