[clang] [llvm] Remove Native Client support (PR #133661)
Brad Smith via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 30 17:07:16 PDT 2025
https://github.com/brad0 updated https://github.com/llvm/llvm-project/pull/133661
>From f692c4f5c1c88f93c13bf960d836de5c0aa96632 Mon Sep 17 00:00:00 2001
From: Brad Smith <brad at comstyle.com>
Date: Sat, 29 Mar 2025 22:11:41 -0400
Subject: [PATCH] Remove Native Client support
---
clang/include/clang/Basic/TargetInfo.h | 4 -
clang/lib/AST/ASTContext.cpp | 10 -
clang/lib/Basic/CMakeLists.txt | 1 -
clang/lib/Basic/Targets.cpp | 12 -
clang/lib/Basic/Targets/ARM.cpp | 3 -
clang/lib/Basic/Targets/OSTargets.h | 47 ---
clang/lib/Basic/Targets/PNaCl.cpp | 29 --
clang/lib/Basic/Targets/PNaCl.h | 90 -----
clang/lib/CodeGen/CMakeLists.txt | 1 -
clang/lib/CodeGen/CodeGenModule.cpp | 4 +-
clang/lib/CodeGen/TargetInfo.h | 3 -
clang/lib/CodeGen/Targets/PNaCl.cpp | 114 ------
clang/lib/CodeGen/Targets/X86.cpp | 3 +-
clang/lib/Driver/CMakeLists.txt | 1 -
clang/lib/Driver/Driver.cpp | 4 -
clang/lib/Driver/ToolChains/NaCl.cpp | 371 ------------------
clang/lib/Driver/ToolChains/NaCl.h | 88 -----
clang/lib/Lex/InitHeaderSearch.cpp | 1 -
.../test/CodeGen/X86/x86_64-arguments-nacl.c | 92 -----
clang/test/CodeGen/X86/x86_64-longdouble.c | 16 -
clang/test/CodeGen/arm-aapcs-vfp.c | 6 -
clang/test/CodeGen/ext-int-cc.c | 9 -
clang/test/CodeGen/long_double_fp128.cpp | 4 -
clang/test/CodeGen/malign-double-x86-nacl.c | 43 --
clang/test/CodeGen/target-data.c | 16 -
.../CodeGenCXX/x86_64-arguments-nacl-x32.cpp | 57 ---
clang/test/Driver/arm-alignment.c | 6 -
clang/test/Driver/nacl-direct.c | 146 -------
clang/test/Driver/unsupported-target-arch.c | 4 -
clang/test/Driver/x86_64-nacl-defines.cpp | 45 ---
clang/test/Frontend/x86_64-nacl-types.cpp | 37 --
.../predefined-macros-no-warnings.c | 4 -
llvm/include/llvm/BinaryFormat/ELF.h | 1 -
.../llvm/BinaryFormat/MinidumpConstants.def | 1 -
llvm/include/llvm/CodeGen/AtomicExpandUtils.h | 3 +-
llvm/include/llvm/TargetParser/Triple.h | 6 -
llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 6 -
llvm/lib/Target/ARM/ARMFastISel.cpp | 8 +-
llvm/lib/Target/ARM/ARMFeatures.td | 6 -
llvm/lib/Target/ARM/ARMFrameLowering.cpp | 4 +-
llvm/lib/Target/ARM/ARMISelLowering.cpp | 7 +-
llvm/lib/Target/ARM/ARMInstrInfo.td | 20 +-
llvm/lib/Target/ARM/ARMPredicates.td | 4 -
llvm/lib/Target/ARM/ARMSubtarget.cpp | 9 +-
llvm/lib/Target/ARM/ARMSubtarget.h | 1 -
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 5 +-
llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 6 +-
.../ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 6 -
.../Target/Mips/MCTargetDesc/CMakeLists.txt | 1 -
.../lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h | 31 --
.../Mips/MCTargetDesc/MipsMCTargetDesc.cpp | 9 +-
.../Mips/MCTargetDesc/MipsNaClELFStreamer.cpp | 274 -------------
llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 31 --
llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 -
llvm/lib/Target/Mips/MipsBranchExpansion.cpp | 25 +-
llvm/lib/Target/Mips/MipsCallingConv.td | 11 +-
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 13 -
llvm/lib/Target/Mips/MipsInstrFPU.td | 18 +-
llvm/lib/Target/Mips/MipsInstrInfo.td | 1 -
llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 7 -
llvm/lib/Target/Mips/MipsSubtarget.h | 1 -
llvm/lib/Target/X86/X86ExpandPseudo.cpp | 3 +-
llvm/lib/Target/X86/X86FrameLowering.cpp | 6 +-
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 -
llvm/lib/Target/X86/X86ISelLowering.cpp | 9 +-
llvm/lib/Target/X86/X86InstrPredicates.td | 2 -
llvm/lib/Target/X86/X86Subtarget.cpp | 5 +-
llvm/lib/Target/X86/X86Subtarget.h | 11 +-
llvm/lib/Target/X86/X86TargetMachine.cpp | 6 +-
llvm/lib/TargetParser/ARMTargetParser.cpp | 1 -
llvm/lib/TargetParser/Triple.cpp | 2 -
llvm/test/CodeGen/ARM/fast-isel-align.ll | 3 -
llvm/test/CodeGen/ARM/struct_byval.ll | 14 -
llvm/test/CodeGen/ARM/trap.ll | 20 -
.../ARM/varargs-spill-stack-align-nacl.ll | 31 --
llvm/test/CodeGen/Mips/fastcc.ll | 12 -
llvm/test/CodeGen/Mips/fp-indexed-ls.ll | 11 -
.../Mips/indirect-jump-hazard/long-branch.ll | 1 -
llvm/test/CodeGen/Mips/longbranch.ll | 38 --
llvm/test/CodeGen/Mips/nacl-align.ll | 99 -----
llvm/test/CodeGen/Mips/nacl-branch-delay.ll | 71 ----
llvm/test/CodeGen/Mips/nacl-reserved-regs.ll | 51 ---
.../CodeGen/Thumb2/pacbti-m-outliner-1.ll | 2 +-
llvm/test/CodeGen/X86/constructor.ll | 13 -
llvm/test/CodeGen/X86/fast-isel-x32.ll | 1 -
llvm/test/CodeGen/X86/frameaddr.ll | 11 -
llvm/test/CodeGen/X86/lea-2.ll | 1 -
llvm/test/CodeGen/X86/lea-3.ll | 1 -
llvm/test/CodeGen/X86/lea-4.ll | 1 -
llvm/test/CodeGen/X86/lea-5.ll | 1 -
llvm/test/CodeGen/X86/lea.ll | 1 -
llvm/test/CodeGen/X86/stack-align2.ll | 5 -
llvm/test/CodeGen/X86/x86-64-baseptr.ll | 8 -
.../CodeGen/X86/x86-64-stack-and-frame-ptr.ll | 9 -
llvm/test/MC/ARM/arm_instructions.s | 6 -
llvm/test/MC/Mips/nacl-mask.s | 319 ---------------
.../test/MC/X86/AlignedBundling/labeloffset.s | 4 -
.../MC/X86/AlignedBundling/rodata-section.s | 30 --
.../TargetParser/TargetParserTest.cpp | 4 -
99 files changed, 49 insertions(+), 2556 deletions(-)
delete mode 100644 clang/lib/Basic/Targets/PNaCl.cpp
delete mode 100644 clang/lib/Basic/Targets/PNaCl.h
delete mode 100644 clang/lib/CodeGen/Targets/PNaCl.cpp
delete mode 100644 clang/lib/Driver/ToolChains/NaCl.cpp
delete mode 100644 clang/lib/Driver/ToolChains/NaCl.h
delete mode 100644 clang/test/CodeGen/X86/x86_64-arguments-nacl.c
delete mode 100644 clang/test/CodeGen/malign-double-x86-nacl.c
delete mode 100644 clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
delete mode 100644 clang/test/Driver/nacl-direct.c
delete mode 100644 clang/test/Driver/x86_64-nacl-defines.cpp
delete mode 100644 clang/test/Frontend/x86_64-nacl-types.cpp
delete mode 100644 llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
delete mode 100644 llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
delete mode 100644 llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
delete mode 100644 llvm/test/CodeGen/Mips/nacl-align.ll
delete mode 100644 llvm/test/CodeGen/Mips/nacl-branch-delay.ll
delete mode 100644 llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
delete mode 100644 llvm/test/MC/Mips/nacl-mask.s
delete mode 100644 llvm/test/MC/X86/AlignedBundling/rodata-section.s
diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h
index 497d68779b92b..3c7f3552e4f49 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -336,10 +336,6 @@ class TargetInfo : public TransferrableTargetInfo,
/// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055a/IHI0055A_aapcs64.pdf
AArch64ABIBuiltinVaList,
- /// __builtin_va_list as defined by the PNaCl ABI:
- /// http://www.chromium.org/nativeclient/pnacl/bitcode-abi#TOC-Machine-Types
- PNaClABIBuiltinVaList,
-
/// __builtin_va_list as defined by the Power ABI:
/// https://www.power.org
/// /resources/downloads/Power-Arch-32-bit-ABI-supp-1.0-Embedded.pdf
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index c9d1bea4c623a..1a63646ab534e 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -9740,14 +9740,6 @@ CreateX86_64ABIBuiltinVaListDecl(const ASTContext *Context) {
return Context->buildImplicitTypedef(VaListTagArrayType, "__builtin_va_list");
}
-static TypedefDecl *CreatePNaClABIBuiltinVaListDecl(const ASTContext *Context) {
- // typedef int __builtin_va_list[4];
- llvm::APInt Size(Context->getTypeSize(Context->getSizeType()), 4);
- QualType IntArrayType = Context->getConstantArrayType(
- Context->IntTy, Size, nullptr, ArraySizeModifier::Normal, 0);
- return Context->buildImplicitTypedef(IntArrayType, "__builtin_va_list");
-}
-
static TypedefDecl *
CreateAAPCSABIBuiltinVaListDecl(const ASTContext *Context) {
// struct __va_list
@@ -9945,8 +9937,6 @@ static TypedefDecl *CreateVaListDecl(const ASTContext *Context,
return CreatePowerABIBuiltinVaListDecl(Context);
case TargetInfo::X86_64ABIBuiltinVaList:
return CreateX86_64ABIBuiltinVaListDecl(Context);
- case TargetInfo::PNaClABIBuiltinVaList:
- return CreatePNaClABIBuiltinVaListDecl(Context);
case TargetInfo::AAPCSABIBuiltinVaList:
return CreateAAPCSABIBuiltinVaListDecl(Context);
case TargetInfo::SystemZBuiltinVaList:
diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt
index 331dfbb3f4b67..bb96e3736941f 100644
--- a/clang/lib/Basic/CMakeLists.txt
+++ b/clang/lib/Basic/CMakeLists.txt
@@ -109,7 +109,6 @@ add_clang_library(clangBasic
Targets/Mips.cpp
Targets/NVPTX.cpp
Targets/OSTargets.cpp
- Targets/PNaCl.cpp
Targets/PPC.cpp
Targets/RISCV.cpp
Targets/SPIR.cpp
diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index c6d228fe98100..d38c2edc7ebf6 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -29,7 +29,6 @@
#include "Targets/Mips.h"
#include "Targets/NVPTX.h"
#include "Targets/OSTargets.h"
-#include "Targets/PNaCl.h"
#include "Targets/PPC.h"
#include "Targets/RISCV.h"
#include "Targets/SPIR.h"
@@ -225,8 +224,6 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
return std::make_unique<RTEMSTargetInfo<ARMleTargetInfo>>(Triple, Opts);
case llvm::Triple::Haiku:
return std::make_unique<HaikuTargetInfo<ARMleTargetInfo>>(Triple, Opts);
- case llvm::Triple::NaCl:
- return std::make_unique<NaClTargetInfo<ARMleTargetInfo>>(Triple, Opts);
case llvm::Triple::Win32:
switch (Triple.getEnvironment()) {
case llvm::Triple::Cygnus:
@@ -257,8 +254,6 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
return std::make_unique<NetBSDTargetInfo<ARMbeTargetInfo>>(Triple, Opts);
case llvm::Triple::RTEMS:
return std::make_unique<RTEMSTargetInfo<ARMbeTargetInfo>>(Triple, Opts);
- case llvm::Triple::NaCl:
- return std::make_unique<NaClTargetInfo<ARMbeTargetInfo>>(Triple, Opts);
default:
return std::make_unique<ARMbeTargetInfo>(Triple, Opts);
}
@@ -301,9 +296,6 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
return std::make_unique<FreeBSDTargetInfo<MipsTargetInfo>>(Triple, Opts);
case llvm::Triple::NetBSD:
return std::make_unique<NetBSDTargetInfo<MipsTargetInfo>>(Triple, Opts);
- case llvm::Triple::NaCl:
- return std::make_unique<NaClTargetInfo<NaClMips32TargetInfo>>(Triple,
- Opts);
case llvm::Triple::Win32:
switch (Triple.getEnvironment()) {
case llvm::Triple::GNU:
@@ -585,8 +577,6 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
return std::make_unique<HaikuX86_32TargetInfo>(Triple, Opts);
case llvm::Triple::RTEMS:
return std::make_unique<RTEMSX86_32TargetInfo>(Triple, Opts);
- case llvm::Triple::NaCl:
- return std::make_unique<NaClTargetInfo<X86_32TargetInfo>>(Triple, Opts);
case llvm::Triple::ELFIAMCU:
return std::make_unique<MCUX86_32TargetInfo>(Triple, Opts);
case llvm::Triple::Hurd:
@@ -646,8 +636,6 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple,
}
case llvm::Triple::Haiku:
return std::make_unique<HaikuTargetInfo<X86_64TargetInfo>>(Triple, Opts);
- case llvm::Triple::NaCl:
- return std::make_unique<NaClTargetInfo<X86_64TargetInfo>>(Triple, Opts);
case llvm::Triple::PS4:
return std::make_unique<PS4OSTargetInfo<X86_64TargetInfo>>(Triple, Opts);
case llvm::Triple::PS5:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index ca2c1ffbb0eb7..518e4ec82ca77 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -58,9 +58,6 @@ void ARMTargetInfo::setABIAAPCS() {
"-a:0:32"
"-n32"
"-S64");
- } else if (T.isOSNaCl()) {
- assert(!BigEndian && "NaCl on ARM does not support big endian");
- resetDataLayout("e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128");
} else {
resetDataLayout(BigEndian
? "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h
index a88c851797aab..dbff025265ee6 100644
--- a/clang/lib/Basic/Targets/OSTargets.h
+++ b/clang/lib/Basic/Targets/OSTargets.h
@@ -842,53 +842,6 @@ class LLVM_LIBRARY_VISIBILITY WindowsTargetInfo : public OSTargetInfo<Target> {
}
};
-template <typename Target>
-class LLVM_LIBRARY_VISIBILITY NaClTargetInfo : public OSTargetInfo<Target> {
-protected:
- void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
- MacroBuilder &Builder) const override {
- if (Opts.POSIXThreads)
- Builder.defineMacro("_REENTRANT");
- if (Opts.CPlusPlus)
- Builder.defineMacro("_GNU_SOURCE");
-
- DefineStd(Builder, "unix", Opts);
- Builder.defineMacro("__native_client__");
- }
-
-public:
- NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
- : OSTargetInfo<Target>(Triple, Opts) {
- this->LongAlign = 32;
- this->LongWidth = 32;
- this->PointerAlign = 32;
- this->PointerWidth = 32;
- this->IntMaxType = TargetInfo::SignedLongLong;
- this->Int64Type = TargetInfo::SignedLongLong;
- this->DoubleAlign = 64;
- this->LongDoubleWidth = 64;
- this->LongDoubleAlign = 64;
- this->LongLongWidth = 64;
- this->LongLongAlign = 64;
- this->SizeType = TargetInfo::UnsignedInt;
- this->PtrDiffType = TargetInfo::SignedInt;
- this->IntPtrType = TargetInfo::SignedInt;
- // RegParmMax is inherited from the underlying architecture.
- this->LongDoubleFormat = &llvm::APFloat::IEEEdouble();
- if (Triple.getArch() == llvm::Triple::arm) {
- // Handled in ARM's setABI().
- } else if (Triple.getArch() == llvm::Triple::x86) {
- this->resetDataLayout("e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-"
- "i64:64-i128:128-n8:16:32-S128");
- } else if (Triple.getArch() == llvm::Triple::x86_64) {
- this->resetDataLayout("e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-"
- "i64:64-i128:128-n8:16:32:64-S128");
- } else if (Triple.getArch() == llvm::Triple::mipsel) {
- // Handled on mips' setDataLayout.
- }
- }
-};
-
// Fuchsia Target
template <typename Target>
class LLVM_LIBRARY_VISIBILITY FuchsiaTargetInfo : public OSTargetInfo<Target> {
diff --git a/clang/lib/Basic/Targets/PNaCl.cpp b/clang/lib/Basic/Targets/PNaCl.cpp
deleted file mode 100644
index c4adfbefb9c73..0000000000000
--- a/clang/lib/Basic/Targets/PNaCl.cpp
+++ /dev/null
@@ -1,29 +0,0 @@
-//===--- PNaCl.cpp - Implement PNaCl target feature support ---------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements PNaCl TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#include "PNaCl.h"
-#include "clang/Basic/MacroBuilder.h"
-
-using namespace clang;
-using namespace clang::targets;
-
-ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { return {}; }
-
-ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
- return {};
-}
-
-void PNaClTargetInfo::getArchDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
- Builder.defineMacro("__le32__");
- Builder.defineMacro("__pnacl__");
-}
diff --git a/clang/lib/Basic/Targets/PNaCl.h b/clang/lib/Basic/Targets/PNaCl.h
deleted file mode 100644
index d162776b5a0d6..0000000000000
--- a/clang/lib/Basic/Targets/PNaCl.h
+++ /dev/null
@@ -1,90 +0,0 @@
-//===--- PNaCl.h - Declare PNaCl target feature support ---------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares PNaCl TargetInfo objects.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H
-#define LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H
-
-#include "Mips.h"
-#include "clang/Basic/TargetInfo.h"
-#include "clang/Basic/TargetOptions.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/TargetParser/Triple.h"
-
-namespace clang {
-namespace targets {
-
-class LLVM_LIBRARY_VISIBILITY PNaClTargetInfo : public TargetInfo {
-public:
- PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
- : TargetInfo(Triple) {
- this->LongAlign = 32;
- this->LongWidth = 32;
- this->PointerAlign = 32;
- this->PointerWidth = 32;
- this->IntMaxType = TargetInfo::SignedLongLong;
- this->Int64Type = TargetInfo::SignedLongLong;
- this->DoubleAlign = 64;
- this->LongDoubleWidth = 64;
- this->LongDoubleAlign = 64;
- this->SizeType = TargetInfo::UnsignedInt;
- this->PtrDiffType = TargetInfo::SignedInt;
- this->IntPtrType = TargetInfo::SignedInt;
- this->RegParmMax = 0; // Disallow regparm
- }
-
- void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const;
-
- void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override {
- getArchDefines(Opts, Builder);
- }
-
- bool hasFeature(StringRef Feature) const override {
- return Feature == "pnacl";
- }
-
- llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override {
- return {};
- }
-
- BuiltinVaListKind getBuiltinVaListKind() const override {
- return TargetInfo::PNaClABIBuiltinVaList;
- }
-
- ArrayRef<const char *> getGCCRegNames() const override;
-
- ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
-
- bool validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
- return false;
- }
-
- std::string_view getClobbers() const override { return ""; }
-
- bool hasBitIntType() const override { return true; }
-};
-
-// We attempt to use PNaCl (le32) frontend and Mips32EL backend.
-class LLVM_LIBRARY_VISIBILITY NaClMips32TargetInfo : public MipsTargetInfo {
-public:
- NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
- : MipsTargetInfo(Triple, Opts) {}
-
- BuiltinVaListKind getBuiltinVaListKind() const override {
- return TargetInfo::PNaClABIBuiltinVaList;
- }
-};
-} // namespace targets
-} // namespace clang
-
-#endif // LLVM_CLANG_LIB_BASIC_TARGETS_PNACL_H
diff --git a/clang/lib/CodeGen/CMakeLists.txt b/clang/lib/CodeGen/CMakeLists.txt
index ebe2fbd7db295..51769fe895ee3 100644
--- a/clang/lib/CodeGen/CMakeLists.txt
+++ b/clang/lib/CodeGen/CMakeLists.txt
@@ -142,7 +142,6 @@ add_clang_library(clangCodeGen
Targets/MSP430.cpp
Targets/Mips.cpp
Targets/NVPTX.cpp
- Targets/PNaCl.cpp
Targets/PPC.cpp
Targets/RISCV.cpp
Targets/SPIR.cpp
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 5dbd50be6ca1a..2041c5fd0f68a 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -118,9 +118,7 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
return createM68kTargetCodeGenInfo(CGM);
case llvm::Triple::mips:
case llvm::Triple::mipsel:
- if (Triple.getOS() == llvm::Triple::NaCl)
- return createPNaClTargetCodeGenInfo(CGM);
- else if (Triple.getOS() == llvm::Triple::Win32)
+ if (Triple.getOS() == llvm::Triple::Win32)
return createWindowsMIPSTargetCodeGenInfo(CGM, /*IsOS32=*/true);
return createMIPSTargetCodeGenInfo(CGM, /*IsOS32=*/true);
diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h
index 5df19fbef1e5b..44dab29b3ea86 100644
--- a/clang/lib/CodeGen/TargetInfo.h
+++ b/clang/lib/CodeGen/TargetInfo.h
@@ -533,9 +533,6 @@ createMSP430TargetCodeGenInfo(CodeGenModule &CGM);
std::unique_ptr<TargetCodeGenInfo>
createNVPTXTargetCodeGenInfo(CodeGenModule &CGM);
-std::unique_ptr<TargetCodeGenInfo>
-createPNaClTargetCodeGenInfo(CodeGenModule &CGM);
-
enum class PPC64_SVR4_ABIKind {
ELFv1 = 0,
ELFv2,
diff --git a/clang/lib/CodeGen/Targets/PNaCl.cpp b/clang/lib/CodeGen/Targets/PNaCl.cpp
deleted file mode 100644
index 358010785850e..0000000000000
--- a/clang/lib/CodeGen/Targets/PNaCl.cpp
+++ /dev/null
@@ -1,114 +0,0 @@
-//===- PNaCl.cpp ----------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "ABIInfoImpl.h"
-#include "TargetInfo.h"
-
-using namespace clang;
-using namespace clang::CodeGen;
-
-//===----------------------------------------------------------------------===//
-// le32/PNaCl bitcode ABI Implementation
-//
-// This is a simplified version of the x86_32 ABI. Arguments and return values
-// are always passed on the stack.
-//===----------------------------------------------------------------------===//
-
-class PNaClABIInfo : public ABIInfo {
- public:
- PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {}
-
- ABIArgInfo classifyReturnType(QualType RetTy) const;
- ABIArgInfo classifyArgumentType(QualType RetTy) const;
-
- void computeInfo(CGFunctionInfo &FI) const override;
- RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
- AggValueSlot Slot) const override;
-};
-
-class PNaClTargetCodeGenInfo : public TargetCodeGenInfo {
- public:
- PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
- : TargetCodeGenInfo(std::make_unique<PNaClABIInfo>(CGT)) {}
-};
-
-void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const {
- if (!getCXXABI().classifyReturnType(FI))
- FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
-
- for (auto &I : FI.arguments())
- I.info = classifyArgumentType(I.type);
-}
-
-RValue PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
- QualType Ty, AggValueSlot Slot) const {
- // The PNaCL ABI is a bit odd, in that varargs don't use normal
- // function classification. Structs get passed directly for varargs
- // functions, through a rewriting transform in
- // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows
- // this target to actually support a va_arg instructions with an
- // aggregate type, unlike other targets.
- return CGF.EmitLoadOfAnyValue(
- CGF.MakeAddrLValue(
- EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect()), Ty),
- Slot);
-}
-
-/// Classify argument of given type \p Ty.
-ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const {
- if (isAggregateTypeForABI(Ty)) {
- if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI()))
- return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),
- RAA == CGCXXABI::RAA_DirectInMemory);
- return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace());
- } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) {
- // Treat an enum type as its underlying type.
- Ty = EnumTy->getDecl()->getIntegerType();
- } else if (Ty->isFloatingType()) {
- // Floating-point types don't go inreg.
- return ABIArgInfo::getDirect();
- } else if (const auto *EIT = Ty->getAs<BitIntType>()) {
- // Treat bit-precise integers as integers if <= 64, otherwise pass
- // indirectly.
- if (EIT->getNumBits() > 64)
- return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace());
- return ABIArgInfo::getDirect();
- }
-
- return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
-}
-
-ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const {
- if (RetTy->isVoidType())
- return ABIArgInfo::getIgnore();
-
- // In the PNaCl ABI we always return records/structures on the stack.
- if (isAggregateTypeForABI(RetTy))
- return getNaturalAlignIndirect(RetTy, getDataLayout().getAllocaAddrSpace());
-
- // Treat bit-precise integers as integers if <= 64, otherwise pass indirectly.
- if (const auto *EIT = RetTy->getAs<BitIntType>()) {
- if (EIT->getNumBits() > 64)
- return getNaturalAlignIndirect(RetTy,
- getDataLayout().getAllocaAddrSpace());
- return ABIArgInfo::getDirect();
- }
-
- // Treat an enum type as its underlying type.
- if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
- RetTy = EnumTy->getDecl()->getIntegerType();
-
- return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
- : ABIArgInfo::getDirect());
-}
-
-std::unique_ptr<TargetCodeGenInfo>
-CodeGen::createPNaClTargetCodeGenInfo(CodeGenModule &CGM) {
- return std::make_unique<PNaClTargetCodeGenInfo>(CGM.getTypes());
-}
diff --git a/clang/lib/CodeGen/Targets/X86.cpp b/clang/lib/CodeGen/Targets/X86.cpp
index b36a6e1396653..606e5ce780bd0 100644
--- a/clang/lib/CodeGen/Targets/X86.cpp
+++ b/clang/lib/CodeGen/Targets/X86.cpp
@@ -2573,8 +2573,7 @@ GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
if (HiStart != 8) {
// There are usually two sorts of types the ABI generation code can produce
// for the low part of a pair that aren't 8 bytes in size: half, float or
- // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
- // NaCl).
+ // i8/i16/i32. This can also include pointers when they are 32-bit (X32).
// Promote these to a larger type.
if (Lo->isHalfTy() || Lo->isFloatTy())
Lo = llvm::Type::getDoubleTy(Lo->getContext());
diff --git a/clang/lib/Driver/CMakeLists.txt b/clang/lib/Driver/CMakeLists.txt
index 5bdb6614389cf..306d6f689ef0a 100644
--- a/clang/lib/Driver/CMakeLists.txt
+++ b/clang/lib/Driver/CMakeLists.txt
@@ -69,7 +69,6 @@ add_clang_library(clangDriver
ToolChains/MinGW.cpp
ToolChains/MSP430.cpp
ToolChains/MSVC.cpp
- ToolChains/NaCl.cpp
ToolChains/NetBSD.cpp
ToolChains/OHOS.cpp
ToolChains/OpenBSD.cpp
diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp
index 07e36ea2efba4..31569f7138d3b 100644
--- a/clang/lib/Driver/Driver.cpp
+++ b/clang/lib/Driver/Driver.cpp
@@ -34,7 +34,6 @@
#include "ToolChains/MSVC.h"
#include "ToolChains/MinGW.h"
#include "ToolChains/MipsLinux.h"
-#include "ToolChains/NaCl.h"
#include "ToolChains/NetBSD.h"
#include "ToolChains/OHOS.h"
#include "ToolChains/OpenBSD.h"
@@ -6791,9 +6790,6 @@ const ToolChain &Driver::getToolChain(const ArgList &Args,
else
TC = std::make_unique<toolchains::Linux>(*this, Target, Args);
break;
- case llvm::Triple::NaCl:
- TC = std::make_unique<toolchains::NaClToolChain>(*this, Target, Args);
- break;
case llvm::Triple::Fuchsia:
TC = std::make_unique<toolchains::Fuchsia>(*this, Target, Args);
break;
diff --git a/clang/lib/Driver/ToolChains/NaCl.cpp b/clang/lib/Driver/ToolChains/NaCl.cpp
deleted file mode 100644
index 22f038e5152ff..0000000000000
--- a/clang/lib/Driver/ToolChains/NaCl.cpp
+++ /dev/null
@@ -1,371 +0,0 @@
-//===--- NaCl.cpp - Native Client ToolChain Implementations -----*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "NaCl.h"
-#include "CommonArgs.h"
-#include "clang/Driver/Compilation.h"
-#include "clang/Driver/Driver.h"
-#include "clang/Driver/DriverDiagnostic.h"
-#include "clang/Driver/InputInfo.h"
-#include "clang/Driver/Options.h"
-#include "llvm/Option/ArgList.h"
-#include "llvm/Support/Path.h"
-
-using namespace clang::driver;
-using namespace clang::driver::tools;
-using namespace clang::driver::toolchains;
-using namespace clang;
-using namespace llvm::opt;
-
-// NaCl ARM assembly (inline or standalone) can be written with a set of macros
-// for the various SFI requirements like register masking. The assembly tool
-// inserts the file containing the macros as an input into all the assembly
-// jobs.
-void nacltools::AssemblerARM::ConstructJob(Compilation &C, const JobAction &JA,
- const InputInfo &Output,
- const InputInfoList &Inputs,
- const ArgList &Args,
- const char *LinkingOutput) const {
- const auto &ToolChain = static_cast<const NaClToolChain &>(getToolChain());
- InputInfo NaClMacros(types::TY_PP_Asm, ToolChain.GetNaClArmMacrosPath(),
- "nacl-arm-macros.s");
- InputInfoList NewInputs;
- NewInputs.push_back(NaClMacros);
- NewInputs.append(Inputs.begin(), Inputs.end());
- gnutools::Assembler::ConstructJob(C, JA, Output, NewInputs, Args,
- LinkingOutput);
-}
-
-// This is quite similar to gnutools::Linker::ConstructJob with changes that
-// we use static by default, do not yet support sanitizers or LTO, and a few
-// others. Eventually we can support more of that and hopefully migrate back
-// to gnutools::Linker.
-void nacltools::Linker::ConstructJob(Compilation &C, const JobAction &JA,
- const InputInfo &Output,
- const InputInfoList &Inputs,
- const ArgList &Args,
- const char *LinkingOutput) const {
-
- const auto &ToolChain = static_cast<const NaClToolChain &>(getToolChain());
- const Driver &D = ToolChain.getDriver();
- const llvm::Triple::ArchType Arch = ToolChain.getArch();
- const bool IsStatic =
- !Args.hasArg(options::OPT_dynamic) && !Args.hasArg(options::OPT_shared);
-
- ArgStringList CmdArgs;
-
- // Silence warning for "clang -g foo.o -o foo"
- Args.ClaimAllArgs(options::OPT_g_Group);
- // and "clang -emit-llvm foo.o -o foo"
- Args.ClaimAllArgs(options::OPT_emit_llvm);
- // and for "clang -w foo.o -o foo". Other warning options are already
- // handled somewhere else.
- Args.ClaimAllArgs(options::OPT_w);
-
- if (!D.SysRoot.empty())
- CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
-
- if (Args.hasArg(options::OPT_rdynamic))
- CmdArgs.push_back("-export-dynamic");
-
- if (Args.hasArg(options::OPT_s))
- CmdArgs.push_back("-s");
-
- // NaClToolChain doesn't have ExtraOpts like Linux; the only relevant flag
- // from there is --build-id, which we do want.
- CmdArgs.push_back("--build-id");
-
- if (!IsStatic)
- CmdArgs.push_back("--eh-frame-hdr");
-
- CmdArgs.push_back("-m");
- if (Arch == llvm::Triple::x86)
- CmdArgs.push_back("elf_i386_nacl");
- else if (Arch == llvm::Triple::arm)
- CmdArgs.push_back("armelf_nacl");
- else if (Arch == llvm::Triple::x86_64)
- CmdArgs.push_back("elf_x86_64_nacl");
- else if (Arch == llvm::Triple::mipsel)
- CmdArgs.push_back("mipselelf_nacl");
- else
- D.Diag(diag::err_target_unsupported_arch) << ToolChain.getArchName()
- << "Native Client";
-
- if (IsStatic)
- CmdArgs.push_back("-static");
- else if (Args.hasArg(options::OPT_shared))
- CmdArgs.push_back("-shared");
-
- CmdArgs.push_back("-o");
- CmdArgs.push_back(Output.getFilename());
- if (!Args.hasArg(options::OPT_nostdlib, options::OPT_nostartfiles)) {
- if (!Args.hasArg(options::OPT_shared))
- CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crt1.o")));
- CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crti.o")));
-
- const char *crtbegin;
- if (IsStatic)
- crtbegin = "crtbeginT.o";
- else if (Args.hasArg(options::OPT_shared))
- crtbegin = "crtbeginS.o";
- else
- crtbegin = "crtbegin.o";
- CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtbegin)));
- }
-
- Args.addAllArgs(CmdArgs, {options::OPT_L, options::OPT_u});
-
- ToolChain.AddFilePathLibArgs(Args, CmdArgs);
-
- if (Args.hasArg(options::OPT_Z_Xlinker__no_demangle))
- CmdArgs.push_back("--no-demangle");
-
- AddLinkerInputs(ToolChain, Inputs, Args, CmdArgs, JA);
-
- if (D.CCCIsCXX() &&
- !Args.hasArg(options::OPT_nostdlib, options::OPT_nodefaultlibs)) {
- if (ToolChain.ShouldLinkCXXStdlib(Args)) {
- bool OnlyLibstdcxxStatic =
- Args.hasArg(options::OPT_static_libstdcxx) && !IsStatic;
- if (OnlyLibstdcxxStatic)
- CmdArgs.push_back("-Bstatic");
- ToolChain.AddCXXStdlibLibArgs(Args, CmdArgs);
- if (OnlyLibstdcxxStatic)
- CmdArgs.push_back("-Bdynamic");
- }
- CmdArgs.push_back("-lm");
- }
-
- if (!Args.hasArg(options::OPT_nostdlib)) {
- if (!Args.hasArg(options::OPT_nodefaultlibs)) {
- // Always use groups, since it has no effect on dynamic libraries.
- CmdArgs.push_back("--start-group");
- CmdArgs.push_back("-lc");
- // NaCl's libc++ currently requires libpthread, so just always include it
- // in the group for C++.
- if (Args.hasArg(options::OPT_pthread) ||
- Args.hasArg(options::OPT_pthreads) || D.CCCIsCXX()) {
- // Gold, used by Mips, handles nested groups differently than ld, and
- // without '-lnacl' it prefers symbols from libpthread.a over libnacl.a,
- // which is not a desired behaviour here.
- // See https://sourceware.org/ml/binutils/2015-03/msg00034.html
- if (getToolChain().getArch() == llvm::Triple::mipsel)
- CmdArgs.push_back("-lnacl");
-
- CmdArgs.push_back("-lpthread");
- }
-
- CmdArgs.push_back("-lgcc");
- CmdArgs.push_back("--as-needed");
- if (IsStatic)
- CmdArgs.push_back("-lgcc_eh");
- else
- CmdArgs.push_back("-lgcc_s");
- CmdArgs.push_back("--no-as-needed");
-
- // Mips needs to create and use pnacl_legacy library that contains
- // definitions from bitcode/pnaclmm.c and definitions for
- // __nacl_tp_tls_offset() and __nacl_tp_tdb_offset().
- if (getToolChain().getArch() == llvm::Triple::mipsel)
- CmdArgs.push_back("-lpnacl_legacy");
-
- CmdArgs.push_back("--end-group");
- }
-
- if (!Args.hasArg(options::OPT_nostartfiles)) {
- const char *crtend;
- if (Args.hasArg(options::OPT_shared))
- crtend = "crtendS.o";
- else
- crtend = "crtend.o";
-
- CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath(crtend)));
- CmdArgs.push_back(Args.MakeArgString(ToolChain.GetFilePath("crtn.o")));
- }
- }
-
- const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath());
- C.addCommand(std::make_unique<Command>(JA, *this,
- ResponseFileSupport::AtFileCurCP(),
- Exec, CmdArgs, Inputs, Output));
-}
-
-/// NaCl Toolchain
-NaClToolChain::NaClToolChain(const Driver &D, const llvm::Triple &Triple,
- const ArgList &Args)
- : Generic_ELF(D, Triple, Args) {
-
- // Remove paths added by Generic_GCC. NaCl Toolchain cannot use the
- // default paths, and must instead only use the paths provided
- // with this toolchain based on architecture.
- path_list &file_paths = getFilePaths();
- path_list &prog_paths = getProgramPaths();
-
- file_paths.clear();
- prog_paths.clear();
-
- // Path for library files (libc.a, ...)
- std::string FilePath(getDriver().Dir + "/../");
-
- // Path for tools (clang, ld, etc..)
- std::string ProgPath(getDriver().Dir + "/../");
-
- // Path for toolchain libraries (libgcc.a, ...)
- std::string ToolPath(getDriver().ResourceDir + "/lib/");
-
- switch (Triple.getArch()) {
- case llvm::Triple::x86:
- file_paths.push_back(FilePath + "x86_64-nacl/lib32");
- file_paths.push_back(FilePath + "i686-nacl/usr/lib");
- prog_paths.push_back(ProgPath + "x86_64-nacl/bin");
- file_paths.push_back(ToolPath + "i686-nacl");
- break;
- case llvm::Triple::x86_64:
- file_paths.push_back(FilePath + "x86_64-nacl/lib");
- file_paths.push_back(FilePath + "x86_64-nacl/usr/lib");
- prog_paths.push_back(ProgPath + "x86_64-nacl/bin");
- file_paths.push_back(ToolPath + "x86_64-nacl");
- break;
- case llvm::Triple::arm:
- file_paths.push_back(FilePath + "arm-nacl/lib");
- file_paths.push_back(FilePath + "arm-nacl/usr/lib");
- prog_paths.push_back(ProgPath + "arm-nacl/bin");
- file_paths.push_back(ToolPath + "arm-nacl");
- break;
- case llvm::Triple::mipsel:
- file_paths.push_back(FilePath + "mipsel-nacl/lib");
- file_paths.push_back(FilePath + "mipsel-nacl/usr/lib");
- prog_paths.push_back(ProgPath + "bin");
- file_paths.push_back(ToolPath + "mipsel-nacl");
- break;
- default:
- break;
- }
-
- NaClArmMacrosPath = GetFilePath("nacl-arm-macros.s");
-}
-
-void NaClToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
- ArgStringList &CC1Args) const {
- const Driver &D = getDriver();
- if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc))
- return;
-
- if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
- SmallString<128> P(D.ResourceDir);
- llvm::sys::path::append(P, "include");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- }
-
- if (DriverArgs.hasArg(options::OPT_nostdlibinc))
- return;
-
- SmallString<128> P(D.Dir + "/../");
- switch (getTriple().getArch()) {
- case llvm::Triple::x86:
- // x86 is special because multilib style uses x86_64-nacl/include for libc
- // headers but the SDK wants i686-nacl/usr/include. The other architectures
- // have the same substring.
- llvm::sys::path::append(P, "i686-nacl/usr/include");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- llvm::sys::path::remove_filename(P);
- llvm::sys::path::remove_filename(P);
- llvm::sys::path::remove_filename(P);
- llvm::sys::path::append(P, "x86_64-nacl/include");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- return;
- case llvm::Triple::arm:
- llvm::sys::path::append(P, "arm-nacl/usr/include");
- break;
- case llvm::Triple::x86_64:
- llvm::sys::path::append(P, "x86_64-nacl/usr/include");
- break;
- case llvm::Triple::mipsel:
- llvm::sys::path::append(P, "mipsel-nacl/usr/include");
- break;
- default:
- return;
- }
-
- addSystemInclude(DriverArgs, CC1Args, P.str());
- llvm::sys::path::remove_filename(P);
- llvm::sys::path::remove_filename(P);
- llvm::sys::path::append(P, "include");
- addSystemInclude(DriverArgs, CC1Args, P.str());
-}
-
-void NaClToolChain::AddCXXStdlibLibArgs(const ArgList &Args,
- ArgStringList &CmdArgs) const {
- // Check for -stdlib= flags. We only support libc++ but this consumes the arg
- // if the value is libc++, and emits an error for other values.
- GetCXXStdlibType(Args);
- CmdArgs.push_back("-lc++");
- if (Args.hasArg(options::OPT_fexperimental_library))
- CmdArgs.push_back("-lc++experimental");
-}
-
-void NaClToolChain::addLibCxxIncludePaths(
- const llvm::opt::ArgList &DriverArgs,
- llvm::opt::ArgStringList &CC1Args) const {
- const Driver &D = getDriver();
-
- SmallString<128> P(D.Dir + "/../");
- switch (getTriple().getArch()) {
- default:
- break;
- case llvm::Triple::arm:
- llvm::sys::path::append(P, "arm-nacl/include/c++/v1");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- break;
- case llvm::Triple::x86:
- llvm::sys::path::append(P, "x86_64-nacl/include/c++/v1");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- break;
- case llvm::Triple::x86_64:
- llvm::sys::path::append(P, "x86_64-nacl/include/c++/v1");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- break;
- case llvm::Triple::mipsel:
- llvm::sys::path::append(P, "mipsel-nacl/include/c++/v1");
- addSystemInclude(DriverArgs, CC1Args, P.str());
- break;
- }
-}
-
-ToolChain::CXXStdlibType
-NaClToolChain::GetCXXStdlibType(const ArgList &Args) const {
- if (Arg *A = Args.getLastArg(options::OPT_stdlib_EQ)) {
- StringRef Value = A->getValue();
- if (Value == "libc++")
- return ToolChain::CST_Libcxx;
- getDriver().Diag(clang::diag::err_drv_invalid_stdlib_name)
- << A->getAsString(Args);
- }
-
- return ToolChain::CST_Libcxx;
-}
-
-std::string
-NaClToolChain::ComputeEffectiveClangTriple(const ArgList &Args,
- types::ID InputType) const {
- llvm::Triple TheTriple(ComputeLLVMTriple(Args, InputType));
- if (TheTriple.getArch() == llvm::Triple::arm &&
- TheTriple.getEnvironment() == llvm::Triple::UnknownEnvironment)
- TheTriple.setEnvironment(llvm::Triple::GNUEABIHF);
- return TheTriple.getTriple();
-}
-
-Tool *NaClToolChain::buildLinker() const {
- return new tools::nacltools::Linker(*this);
-}
-
-Tool *NaClToolChain::buildAssembler() const {
- if (getTriple().getArch() == llvm::Triple::arm)
- return new tools::nacltools::AssemblerARM(*this);
- return new tools::gnutools::Assembler(*this);
-}
diff --git a/clang/lib/Driver/ToolChains/NaCl.h b/clang/lib/Driver/ToolChains/NaCl.h
deleted file mode 100644
index 01d4719e7b929..0000000000000
--- a/clang/lib/Driver/ToolChains/NaCl.h
+++ /dev/null
@@ -1,88 +0,0 @@
-//===--- NaCl.h - Native Client ToolChain Implementations -------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_NACL_H
-#define LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_NACL_H
-
-#include "Gnu.h"
-#include "clang/Driver/Tool.h"
-#include "clang/Driver/ToolChain.h"
-
-namespace clang {
-namespace driver {
-namespace tools {
-namespace nacltools {
-class LLVM_LIBRARY_VISIBILITY AssemblerARM : public gnutools::Assembler {
-public:
- AssemblerARM(const ToolChain &TC) : gnutools::Assembler(TC) {}
-
- void ConstructJob(Compilation &C, const JobAction &JA,
- const InputInfo &Output, const InputInfoList &Inputs,
- const llvm::opt::ArgList &TCArgs,
- const char *LinkingOutput) const override;
-};
-
-class LLVM_LIBRARY_VISIBILITY Linker final : public Tool {
-public:
- Linker(const ToolChain &TC) : Tool("NaCl::Linker", "linker", TC) {}
-
- bool hasIntegratedCPP() const override { return false; }
- bool isLinkJob() const override { return true; }
-
- void ConstructJob(Compilation &C, const JobAction &JA,
- const InputInfo &Output, const InputInfoList &Inputs,
- const llvm::opt::ArgList &TCArgs,
- const char *LinkingOutput) const override;
-};
-} // end namespace nacltools
-} // end namespace tools
-
-namespace toolchains {
-
-class LLVM_LIBRARY_VISIBILITY NaClToolChain : public Generic_ELF {
-public:
- NaClToolChain(const Driver &D, const llvm::Triple &Triple,
- const llvm::opt::ArgList &Args);
-
- void
- AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs,
- llvm::opt::ArgStringList &CC1Args) const override;
- void addLibCxxIncludePaths(
- const llvm::opt::ArgList &DriverArgs,
- llvm::opt::ArgStringList &CC1Args) const override;
-
- CXXStdlibType GetCXXStdlibType(const llvm::opt::ArgList &Args) const override;
-
- void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args,
- llvm::opt::ArgStringList &CmdArgs) const override;
-
- bool IsIntegratedAssemblerDefault() const override {
- return getTriple().getArch() == llvm::Triple::mipsel;
- }
-
- // Get the path to the file containing NaCl's ARM macros.
- // It lives in NaClToolChain because the ARMAssembler tool needs a
- // const char * that it can pass around,
- const char *GetNaClArmMacrosPath() const { return NaClArmMacrosPath.c_str(); }
-
- std::string ComputeEffectiveClangTriple(const llvm::opt::ArgList &Args,
- types::ID InputType) const override;
-
-protected:
- Tool *buildLinker() const override;
- Tool *buildAssembler() const override;
-
-private:
- std::string NaClArmMacrosPath;
-};
-
-} // end namespace toolchains
-} // end namespace driver
-} // end namespace clang
-
-#endif // LLVM_CLANG_LIB_DRIVER_TOOLCHAINS_NACL_H
diff --git a/clang/lib/Lex/InitHeaderSearch.cpp b/clang/lib/Lex/InitHeaderSearch.cpp
index bb2a21356fa8f..bb77d4fc37397 100644
--- a/clang/lib/Lex/InitHeaderSearch.cpp
+++ b/clang/lib/Lex/InitHeaderSearch.cpp
@@ -294,7 +294,6 @@ bool InitHeaderSearch::ShouldAddDefaultIncludePaths(
case llvm::Triple::Hurd:
case llvm::Triple::Linux:
case llvm::Triple::LiteOS:
- case llvm::Triple::NaCl:
case llvm::Triple::NetBSD:
case llvm::Triple::OpenBSD:
case llvm::Triple::PS4:
diff --git a/clang/test/CodeGen/X86/x86_64-arguments-nacl.c b/clang/test/CodeGen/X86/x86_64-arguments-nacl.c
deleted file mode 100644
index 4d820aef8fd2d..0000000000000
--- a/clang/test/CodeGen/X86/x86_64-arguments-nacl.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// RUN: %clang_cc1 -triple x86_64-unknown-nacl -emit-llvm -o - %s| FileCheck %s
-#include <stdarg.h>
-// Test for x86-64 structure representation (instead of pnacl representation),
-// in particular for unions. Also crib a few tests from x86 Linux.
-
-union PP_VarValue {
- int as_int;
- double as_double;
- long long as_i64;
-};
-
-struct PP_Var {
- int type;
- int padding;
- union PP_VarValue value;
-};
-
-// CHECK: define{{.*}} { i64, i64 } @f0()
-struct PP_Var f0(void) {
- struct PP_Var result = { 0, 0, 0 };
- return result;
-}
-
-// CHECK-LABEL: define{{.*}} void @f1(i64 %p1.coerce0, i64 %p1.coerce1)
-void f1(struct PP_Var p1) { while(1) {} }
-
-// long doubles are 64 bits on NaCl
-// CHECK-LABEL: define{{.*}} double @f5()
-long double f5(void) {
- return 0;
-}
-
-// CHECK-LABEL: define{{.*}} void @f6(i8 noundef signext %a0, i16 noundef signext %a1, i32 noundef %a2, i64 noundef %a3, ptr noundef %a4)
-void f6(char a0, short a1, int a2, long long a3, void *a4) {
-}
-
-// CHECK-LABEL: define{{.*}} i64 @f8_1()
-// CHECK-LABEL: define{{.*}} void @f8_2(i64 %a0.coerce)
-union u8 {
- long double a;
- int b;
-};
-union u8 f8_1(void) { while (1) {} }
-void f8_2(union u8 a0) {}
-
-// CHECK-LABEL: define{{.*}} i64 @f9()
-struct s9 { int a; int b; int : 0; } f9(void) { while (1) {} }
-
-// CHECK-LABEL: define{{.*}} void @f10(i64 %a0.coerce)
-struct s10 { int a; int b; int : 0; };
-void f10(struct s10 a0) {}
-
-// CHECK-LABEL: define{{.*}} double @f11()
-union { long double a; float b; } f11(void) { while (1) {} }
-
-// CHECK-LABEL: define{{.*}} i32 @f12_0()
-// CHECK-LABEL: define{{.*}} void @f12_1(i32 %a0.coerce)
-struct s12 { int a __attribute__((aligned(16))); };
-struct s12 f12_0(void) { while (1) {} }
-void f12_1(struct s12 a0) {}
-
-// Check that sret parameter is accounted for when checking available integer
-// registers.
-// CHECK: define{{.*}} void @f13(ptr dead_on_unwind noalias writable sret(%struct.s13_0) align 8 %agg.result, i32 noundef %a, i32 noundef %b, i32 noundef %c, i32 noundef %d, ptr noundef byval({{.*}}) align 8 %e, i32 noundef %f)
-
-struct s13_0 { long long f0[3]; };
-struct s13_1 { long long f0[2]; };
-struct s13_0 f13(int a, int b, int c, int d,
- struct s13_1 e, int f) { while (1) {} }
-
-// CHECK-LABEL: define{{.*}} void @f20(ptr noundef byval(%struct.s20) align 32 %x)
-struct __attribute__((aligned(32))) s20 {
- int x;
- int y;
-};
-void f20(struct s20 x) {}
-
-
-// CHECK: declare void @func(i64)
-typedef struct _str {
- union {
- long double a;
- long c;
- };
-} str;
-
-void func(str s);
-str ss;
-void f9122143(void)
-{
- func(ss);
-}
diff --git a/clang/test/CodeGen/X86/x86_64-longdouble.c b/clang/test/CodeGen/X86/x86_64-longdouble.c
index 7446664bef5bb..5287640e4ed30 100644
--- a/clang/test/CodeGen/X86/x86_64-longdouble.c
+++ b/clang/test/CodeGen/X86/x86_64-longdouble.c
@@ -4,9 +4,6 @@
// RUN: | FileCheck %s --check-prefix=GNU --check-prefix=CHECK
// RUN: %clang_cc1 -triple x86_64 -emit-llvm -O -o - %s \
// RUN: | FileCheck %s --check-prefix=GNU --check-prefix=CHECK
-// NaCl is an example of a target for which long double is the same as double.
-// RUN: %clang_cc1 -triple x86_64-nacl -emit-llvm -O -o - %s \
-// RUN: | FileCheck %s --check-prefix=NACL --check-prefix=CHECK
// Android uses fp128 for long double but other x86_64 targets use x86_fp80.
@@ -22,14 +19,12 @@ long double TestLD(long double x) {
return x * x;
// ANDROID: define{{.*}} fp128 @TestLD(fp128 noundef %x)
// GNU: define{{.*}} x86_fp80 @TestLD(x86_fp80 noundef %x)
-// NACL: define{{.*}} double @TestLD(double noundef %x)
}
long double _Complex TestLDC(long double _Complex x) {
return x * x;
// ANDROID: define{{.*}} void @TestLDC(ptr {{.*}}, ptr {{.*}} %x)
// GNU: define{{.*}} { x86_fp80, x86_fp80 } @TestLDC(ptr {{.*}} %x)
-// NACL: define{{.*}} { double, double } @TestLDC(double noundef %x{{.*}}, double noundef %x{{.*}})
}
typedef __builtin_va_list va_list;
@@ -60,14 +55,11 @@ long double TestGetVarLD(va_list ap) {
// memory.
// ANDROID: define{{.*}} fp128 @TestGetVarLD(
// GNU: define{{.*}} x86_fp80 @TestGetVarLD(
-// NACL: define{{.*}} double @TestGetVarLD(
// ANDROID: br label
// ANDROID: br label
-// NACL: br
// ANDROID: = phi
// GNU-NOT: br
// GNU-NOT: = phi
-// NACL: = phi
// ANDROID: ret fp128
// GNU: ret x86_fp80
}
@@ -78,16 +70,12 @@ long double _Complex TestGetVarLDC(va_list ap) {
// ANDROID: define{{.*}} void @TestGetVarLDC(ptr {{.*}}, ptr
// GNU: define{{.*}} { x86_fp80, x86_fp80 } @TestGetVarLDC(
// Pair of double can go in SSE registers or memory
-// NACL: define{{.*}} { double, double } @TestGetVarLDC(
// ANDROID-NOT: br
// GNU-NOT: br
-// NACL: br
// ANDROID-NOT: phi
// GNU-NOT: phi
-// NACL: phi
// ANDROID: ret void
// GNU: ret { x86_fp80, x86_fp80 }
-// NACL: ret { double, double }
}
void TestVarArg(const char *s, ...);
@@ -116,8 +104,6 @@ void TestPassVarLD(long double x) {
// ANDROID: call {{.*}} @TestVarArg(ptr {{.*}}, fp128 noundef %x
// GNU: define{{.*}} void @TestPassVarLD(x86_fp80 noundef %x)
// GNU: call {{.*}} @TestVarArg(ptr {{.*}}, x86_fp80 noundef %x
-// NACL: define{{.*}} void @TestPassVarLD(double noundef %x)
-// NACL: call {{.*}} @TestVarArg(ptr {{.*}}, double noundef %x
}
void TestPassVarLDC(long double _Complex x) {
@@ -130,6 +116,4 @@ void TestPassVarLDC(long double _Complex x) {
// GNU: store x86_fp80 %{{.*}}, ptr %
// GNU-NEXT: store x86_fp80 %{{.*}}, ptr %
// GNU-NEXT: call {{.*}} @TestVarArg(ptr {{.*}}, ptr {{.*}} %
-// NACL: define{{.*}} void @TestPassVarLDC(double noundef %x{{.*}}, double noundef %x{{.*}})
-// NACL: call {{.*}} @TestVarArg(ptr {{.*}}, double noundef %x{{.*}}, double noundef %x{{.*}})
}
diff --git a/clang/test/CodeGen/arm-aapcs-vfp.c b/clang/test/CodeGen/arm-aapcs-vfp.c
index 9fae33f476d35..6581929f99f14 100644
--- a/clang/test/CodeGen/arm-aapcs-vfp.c
+++ b/clang/test/CodeGen/arm-aapcs-vfp.c
@@ -5,12 +5,6 @@
// RUN: -ffreestanding \
// RUN: -emit-llvm -w -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple armv7-unknown-nacl-gnueabi \
-// RUN: -target-cpu cortex-a8 \
-// RUN: -mfloat-abi hard \
-// RUN: -ffreestanding \
-// RUN: -emit-llvm -w -o - %s | FileCheck %s
-
// RUN: %clang_cc1 -triple arm64-apple-darwin9 -target-feature +neon \
// RUN: -ffreestanding \
// RUN: -emit-llvm -w -o - %s | FileCheck -check-prefix=CHECK64 %s
diff --git a/clang/test/CodeGen/ext-int-cc.c b/clang/test/CodeGen/ext-int-cc.c
index 14efd54e24ffb..1821ac21d1178 100644
--- a/clang/test/CodeGen/ext-int-cc.c
+++ b/clang/test/CodeGen/ext-int-cc.c
@@ -36,7 +36,6 @@ void ParamPassing(_BitInt(128) b, _BitInt(64) c) {}
// WIN64: define dso_local void @ParamPassing(ptr %{{.+}}, i64 %{{.+}})
// LIN32: define{{.*}} void @ParamPassing(ptr %{{.+}}, i64 %{{.+}})
// WIN32: define dso_local void @ParamPassing(ptr %{{.+}}, i64 %{{.+}})
-// NACL: define{{.*}} void @ParamPassing(ptr byval(i128) align 8 %{{.+}}, i64 %{{.+}})
// NVPTX64: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
// NVPTX: define{{.*}} void @ParamPassing(ptr byval(i128) align 8 %{{.+}}, i64 %{{.+}})
// SPARCV9: define{{.*}} void @ParamPassing(i128 %{{.+}}, i64 %{{.+}})
@@ -67,7 +66,6 @@ void ParamPassing2(_BitInt(127) b, _BitInt(63) c) {}
// WIN64: define dso_local void @ParamPassing2(ptr %{{.+}}, i63 %{{.+}})
// LIN32: define{{.*}} void @ParamPassing2(ptr %{{.+}}, i63 %{{.+}})
// WIN32: define dso_local void @ParamPassing2(ptr %{{.+}}, i63 %{{.+}})
-// NACL: define{{.*}} void @ParamPassing2(ptr byval(i128) align 8 %{{.+}}, i63 %{{.+}})
// NVPTX64: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 %{{.+}})
// NVPTX: define{{.*}} void @ParamPassing2(ptr byval(i128) align 8 %{{.+}}, i63 %{{.+}})
// SPARCV9: define{{.*}} void @ParamPassing2(i127 %{{.+}}, i63 signext %{{.+}})
@@ -99,7 +97,6 @@ void ParamPassing3(_BitInt(15) a, _BitInt(31) b) {}
// WIN64: define dso_local void @ParamPassing3(i15 %{{.+}}, i31 %{{.+}})
// LIN32: define{{.*}} void @ParamPassing3(i15 signext %{{.+}}, i31 signext %{{.+}})
// WIN32: define dso_local void @ParamPassing3(i15 signext %{{.+}}, i31 signext %{{.+}})
-// NACL: define{{.*}} void @ParamPassing3(i15 %{{.+}}, i31 %{{.+}})
// NVPTX64: define{{.*}} void @ParamPassing3(i15 signext %{{.+}}, i31 signext %{{.+}})
// NVPTX: define{{.*}} void @ParamPassing3(i15 signext %{{.+}}, i31 signext %{{.+}})
// SPARCV9: define{{.*}} void @ParamPassing3(i15 signext %{{.+}}, i31 signext %{{.+}})
@@ -136,7 +133,6 @@ void ParamPassing4(_BitInt(129) a) {}
// LIN32: define{{.*}} void @ParamPassing4(ptr %{{.+}})
// WIN32: define dso_local void @ParamPassing4(ptr %{{.+}})
// AARCH64: define{{.*}} void @ParamPassing4(ptr %{{.+}})
-// NACL-NOT: define{{.*}} void @ParamPassing4(ptr byval(i129) align 8 %{{.+}})
// NVPTX64-NOT: define{{.*}} void @ParamPassing4(ptr byval(i129) align 8 %{{.+}})
// NVPTX-NOT: define{{.*}} void @ParamPassing4(ptr byval(i129) align 8 %{{.+}})
// SPARCV9-NOT: define{{.*}} void @ParamPassing4(ptr %{{.+}})
@@ -167,7 +163,6 @@ _BitInt(63) ReturnPassing(void) { return 0; }
// WIN64: define dso_local i63 @ReturnPassing(
// LIN32: define{{.*}} i63 @ReturnPassing(
// WIN32: define dso_local i63 @ReturnPassing(
-// NACL: define{{.*}} i63 @ReturnPassing(
// NVPTX64: define{{.*}} i63 @ReturnPassing(
// NVPTX: define{{.*}} i63 @ReturnPassing(
// SPARCV9: define{{.*}} signext i63 @ReturnPassing(
@@ -198,7 +193,6 @@ _BitInt(64) ReturnPassing2(void) { return 0; }
// WIN64: define dso_local i64 @ReturnPassing2(
// LIN32: define{{.*}} i64 @ReturnPassing2(
// WIN32: define dso_local i64 @ReturnPassing2(
-// NACL: define{{.*}} i64 @ReturnPassing2(
// NVPTX64: define{{.*}} i64 @ReturnPassing2(
// NVPTX: define{{.*}} i64 @ReturnPassing2(
// SPARCV9: define{{.*}} i64 @ReturnPassing2(
@@ -229,7 +223,6 @@ _BitInt(127) ReturnPassing3(void) { return 0; }
// WIN64: define dso_local void @ReturnPassing3(ptr dead_on_unwind noalias writable sret
// LIN32: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret
// WIN32: define dso_local void @ReturnPassing3(ptr dead_on_unwind noalias writable sret
-// NACL: define{{.*}} void @ReturnPassing3(ptr dead_on_unwind noalias writable sret
// NVPTX/64 makes the intentional choice to put all return values direct, even
// large structures, so we do the same here.
// NVPTX64: define{{.*}} i127 @ReturnPassing3(
@@ -262,7 +255,6 @@ _BitInt(128) ReturnPassing4(void) { return 0; }
// WIN64: define dso_local void @ReturnPassing4(ptr dead_on_unwind noalias writable sret
// LIN32: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret
// WIN32: define dso_local void @ReturnPassing4(ptr dead_on_unwind noalias writable sret
-// NACL: define{{.*}} void @ReturnPassing4(ptr dead_on_unwind noalias writable sret
// NVPTX64: define{{.*}} i128 @ReturnPassing4(
// NVPTX: define{{.*}} i128 @ReturnPassing4(
// SPARCV9: define{{.*}} i128 @ReturnPassing4(
@@ -295,7 +287,6 @@ _BitInt(129) ReturnPassing5(void) { return 0; }
// LIN32: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret
// WIN32: define dso_local void @ReturnPassing5(ptr dead_on_unwind noalias writable sret
// AARCH64: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret
-// NACL-NOT: define{{.*}} void @ReturnPassing5(ptr dead_on_unwind noalias writable sret
// NVPTX64-NOT: define{{.*}} i129 @ReturnPassing5(
// NVPTX-NOT: define{{.*}} i129 @ReturnPassing5(
// SPARCV9-NOT: define{{.*}} i129 @ReturnPassing5(
diff --git a/clang/test/CodeGen/long_double_fp128.cpp b/clang/test/CodeGen/long_double_fp128.cpp
index 01c81f5d71502..a66e5c5be585f 100644
--- a/clang/test/CodeGen/long_double_fp128.cpp
+++ b/clang/test/CodeGen/long_double_fp128.cpp
@@ -10,12 +10,9 @@
// RUN: | FileCheck %s --check-prefix=G32
// RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm -o - %s \
// RUN: | FileCheck %s --check-prefix=P32
-// RUN: %clang_cc1 -triple x86_64-nacl -emit-llvm -o - %s \
-// RUN: | FileCheck %s --check-prefix=N64
// Check mangled name of long double.
// Android's gcc and llvm use fp128 for long double.
-// NaCl uses double format for long double, but still has separate overloads.
void test(long, float, double, long double, long double _Complex) { }
// A64: define{{.*}} void @_Z4testlfdgCg(i64 noundef %0, float noundef %1, double noundef %2, fp128 noundef %3, ptr
// G64: define{{.*}} void @_Z4testlfdeCe(i64 noundef %0, float noundef %1, double noundef %2, x86_fp80 noundef %3, ptr
@@ -23,4 +20,3 @@ void test(long, float, double, long double, long double _Complex) { }
// A32: define{{.*}} void @_Z4testlfdeCe(i32 noundef %0, float noundef %1, double noundef %2, double noundef %3, ptr
// G32: define{{.*}} void @_Z4testlfdeCe(i32 noundef %0, float noundef %1, double noundef %2, x86_fp80 noundef %3, ptr
// P32: define{{.*}} void @_Z4testlfdgCg(i32 noundef %0, float noundef %1, double noundef %2, ppc_fp128 noundef %3, ptr
-// N64: define{{.*}} void @_Z4testlfdeCe(i32 noundef %0, float noundef %1, double noundef %2, double noundef %3, double noundef {{.*}}, double
diff --git a/clang/test/CodeGen/malign-double-x86-nacl.c b/clang/test/CodeGen/malign-double-x86-nacl.c
deleted file mode 100644
index a415a46221f8b..0000000000000
--- a/clang/test/CodeGen/malign-double-x86-nacl.c
+++ /dev/null
@@ -1,43 +0,0 @@
-// RUN: %clang_cc1 %s -emit-llvm -o - -triple=i686-unknown-nacl | FileCheck %s
-// Check that i686-nacl essentially has -malign-double, which aligns
-// double, long double, and long long to 64-bits.
-
-int checksize[sizeof(long double) == 8 ? 1 : -1];
-int checkalign[__alignof(long double) == 8 ? 1 : -1];
-
-// CHECK-LABEL: define{{.*}} void @s1(double noundef %a)
-void s1(long double a) {}
-
-struct st_ld {
- char c;
- long double ld;
-};
-int checksize2[sizeof(struct st_ld) == 16 ? 1 : -1];
-int checkalign2[__alignof(struct st_ld) == 8 ? 1 : -1];
-
-int checksize3[sizeof(double) == 8 ? 1 : -1];
-int checkalign3[__alignof(double) == 8 ? 1 : -1];
-
-// CHECK-LABEL: define{{.*}} void @s2(double noundef %a)
-void s2(double a) {}
-
-struct st_d {
- char c;
- double d;
-};
-int checksize4[sizeof(struct st_d) == 16 ? 1 : -1];
-int checkalign4[__alignof(struct st_d) == 8 ? 1 : -1];
-
-
-int checksize5[sizeof(long long) == 8 ? 1 : -1];
-int checkalign5[__alignof(long long) == 8 ? 1 : -1];
-
-// CHECK-LABEL: define{{.*}} void @s3(i64 noundef %a)
-void s3(long long a) {}
-
-struct st_ll {
- char c;
- long long ll;
-};
-int checksize6[sizeof(struct st_ll) == 16 ? 1 : -1];
-int checkalign6[__alignof(struct st_ll) == 8 ? 1 : -1];
diff --git a/clang/test/CodeGen/target-data.c b/clang/test/CodeGen/target-data.c
index fe29aadb1dd53..99f669eb6f45d 100644
--- a/clang/test/CodeGen/target-data.c
+++ b/clang/test/CodeGen/target-data.c
@@ -90,22 +90,6 @@
// RUN: FileCheck %s -check-prefix=PS3
// PS3: target datalayout = "E-m:e-p:32:32-Fi64-i64:64-i128:128-n32:64"
-// RUN: %clang_cc1 -triple i686-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=I686-NACL
-// I686-NACL: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n8:16:32-S128"
-
-// RUN: %clang_cc1 -triple x86_64-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=X86_64-NACL
-// X86_64-NACL: target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n8:16:32:64-S128"
-
-// RUN: %clang_cc1 -triple arm-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=ARM-NACL
-// ARM-NACL: target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S128"
-
-// RUN: %clang_cc1 -triple mipsel-nacl -o - -emit-llvm %s | \
-// RUN: FileCheck %s -check-prefix=MIPS-NACL
-// MIPS-NACL: target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
-
// RUN: %clang_cc1 -triple wasm32-unknown-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=WEBASSEMBLY32
// WEBASSEMBLY32: target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
diff --git a/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp b/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
deleted file mode 100644
index f108e528269d6..0000000000000
--- a/clang/test/CodeGenCXX/x86_64-arguments-nacl-x32.cpp
+++ /dev/null
@@ -1,57 +0,0 @@
-// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-nacl -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -std=c++11 -triple=x86_64-unknown-linux-gnux32 -emit-llvm -o - %s | FileCheck %s
-
-struct test_struct {};
-typedef int test_struct::* test_struct_mdp;
-typedef int (test_struct::*test_struct_mfp)();
-
-// CHECK-LABEL: define{{.*}} i32 @{{.*}}f_mdp{{.*}}(i32 %a)
-test_struct_mdp f_mdp(test_struct_mdp a) { return a; }
-
-// CHECK-LABEL: define {{.*}} @{{.*}}f_mfp{{.*}}(i64 %a.coerce)
-test_struct_mfp f_mfp(test_struct_mfp a) { return a; }
-
-// A struct with <= 12 bytes before a member data pointer should still
-// be allowed in registers, since the member data pointer is only 4 bytes.
-// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mdp{{.*}}(i64 %a.coerce0, i64 %a.coerce1)
-struct struct_with_mdp { char *a; char *b; char *c; test_struct_mdp d; };
-void f_struct_with_mdp(struct_with_mdp a) { (void)a; }
-
-struct struct_with_mdp_too_much {
- char *a; char *b; char *c; char *d; test_struct_mdp e;
-};
-// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mdp_too_much{{.*}}({{.*}} byval({{.*}} {{.*}} %a)
-void f_struct_with_mdp_too_much(struct_with_mdp_too_much a) {
- (void)a;
-}
-
-// A struct with <= 8 bytes before a member function pointer should still
-// be allowed in registers, since the member function pointer is only 8 bytes.
-// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mfp_0{{.*}}(i64 %a.coerce0, i32 %a.coerce1)
-struct struct_with_mfp_0 { char *a; test_struct_mfp b; };
-void f_struct_with_mfp_0(struct_with_mfp_0 a) { (void)a; }
-
-// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mfp_1{{.*}}(i64 %a.coerce0, i64 %a.coerce1)
-struct struct_with_mfp_1 { char *a; char *b; test_struct_mfp c; };
-void f_struct_with_mfp_1(struct_with_mfp_1 a) { (void)a; }
-
-// CHECK-LABEL: define{{.*}} void @{{.*}}f_struct_with_mfp_too_much{{.*}}({{.*}} byval({{.*}}) {{.*}} %a, i32 noundef %x)
-struct struct_with_mfp_too_much {
- char *a; char *b; char *c; test_struct_mfp d;
-};
-void f_struct_with_mfp_too_much(struct_with_mfp_too_much a, int x) {
- (void)a;
-}
-
-/* Struct containing an empty struct */
-typedef struct { int* a; test_struct x; double *b; } struct_with_empty;
-
-// CHECK-LABEL: define{{.*}} void @{{.*}}f_pass_struct_with_empty{{.*}}(i64 %x{{.*}}, ptr %x
-void f_pass_struct_with_empty(struct_with_empty x) {
- (void) x;
-}
-
-// CHECK-LABEL: define{{.*}} { i64, ptr } @{{.*}}f_return_struct_with_empty
-struct_with_empty f_return_struct_with_empty() {
- return {0, {}, 0};
-}
diff --git a/clang/test/Driver/arm-alignment.c b/clang/test/Driver/arm-alignment.c
index b714f80a07dc1..3ddf29b31dbda 100644
--- a/clang/test/Driver/arm-alignment.c
+++ b/clang/test/Driver/arm-alignment.c
@@ -16,9 +16,6 @@
// RUN: %clang -target armv7-unknown-linux -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
-// RUN: %clang -target armv7-unknown-nacl-gnueabihf -### %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
-
// RUN: %clang -target armv7-windows -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-UNALIGNED-ARM < %t %s
@@ -80,9 +77,6 @@
// RUN: %clang -target armv6-unknown-linux -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
-// RUN: %clang -target armv6-unknown-nacl-gnueabihf -### %s 2> %t
-// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
-
// RUN: %clang -target armv6m-apple-darwin -### %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ALIGNED-ARM < %t %s
diff --git a/clang/test/Driver/nacl-direct.c b/clang/test/Driver/nacl-direct.c
deleted file mode 100644
index b1a80b3e9f837..0000000000000
--- a/clang/test/Driver/nacl-direct.c
+++ /dev/null
@@ -1,146 +0,0 @@
-// Test clang changes for NaCl Support including:
-// include paths, library paths, emulation, default static
-//
-// RUN: %clang -### %s \
-// RUN: --target=i686-unknown-nacl -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-I686 %s
-// CHECK-I686: "-cc1"
-// CHECK-I686-NOT: "-fno-use-init-array"
-// CHECK-I686: "-target-cpu" "pentium4"
-// CHECK-I686: "-resource-dir" "foo"
-// CHECK-I686: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-I686: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-I686: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-I686: as{{(.exe)?}}" "--32"
-// CHECK-I686: ld{{(.exe)?}}"
-// CHECK-I686: "--build-id"
-// CHECK-I686: "-m" "elf_i386_nacl"
-// CHECK-I686: "-static"
-// CHECK-I686: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}lib32"
-// CHECK-I686: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-I686: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}i686-nacl"
-// CHECK-I686-NOT: -lpthread
-//
-// RUN: %clang -### %s \
-// RUN: --target=x86_64-unknown-nacl -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-x86_64 %s
-// CHECK-x86_64: "-cc1"
-// CHECK-x86_64-NOT: "-fno-use-init-array"
-// CHECK-x86_64: "-target-cpu" "x86-64"
-// CHECK-x86_64: "-resource-dir" "foo"
-// CHECK-x86_64: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-x86_64: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-x86_64: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-x86_64: as{{(.exe)?}}" "--64"
-// CHECK-x86_64: ld{{(.exe)?}}"
-// CHECK-x86_64: "--build-id"
-// CHECK-x86_64: "-m" "elf_x86_64_nacl"
-// CHECK-x86_64: "-static"
-// CHECK-x86_64: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}lib"
-// CHECK-x86_64: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-x86_64: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}x86_64-nacl"
-// CHECK-X86_64-NOT: -lpthread
-//
-// RUN: %clang -### %s \
-// RUN: --target=armv7a-unknown-nacl-gnueabihf -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-ARM %s
-// CHECK-ARM: "-cc1"
-// CHECK-ARM-NOT: "-fno-use-init-array"
-// CHECK-ARM: "-target-cpu" "generic"
-// CHECK-ARM: "-target-abi" "aapcs-linux"
-// CHECK-ARM: "-mfloat-abi" "hard"
-// CHECK-ARM: "-resource-dir" "foo"
-// CHECK-ARM: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-ARM: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-ARM: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}include"
-// CHECK-ARM: as{{(.exe)?}}"
-// CHECK-ARM: "-mfloat-abi=hard"
-// CHECK-ARM: ld{{(.exe)?}}"
-// CHECK-ARM: "--build-id"
-// CHECK-ARM: "-m" "armelf_nacl"
-// CHECK-ARM: "-static"
-// CHECK-ARM: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}lib"
-// CHECK-ARM: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-ARM: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}arm-nacl"
-// CHECK-ARM-NOT: -lpthread
-//
-// RUN: %clang -### %s \
-// RUN: --target=mipsel-unknown-nacl -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-MIPS %s
-// CHECK-MIPS: "-cc1"
-// CHECK-MIPS-NOT: "-fno-use-init-array"
-// CHECK-MIPS: "-target-cpu" "mips32r2"
-// CHECK-MIPS: "-target-abi" "o32"
-// CHECK-MIPS: "-mfloat-abi" "hard"
-// CHECK-MIPS: "-resource-dir" "foo"
-// CHECK-MIPS: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-MIPS: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-MIPS: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}include"
-// CHECK-MIPS-NOT: as{{(.exe)?}}"
-// CHECK-MIPS: ld{{(.exe)?}}"
-// CHECK-MIPS: "--build-id"
-// CHECK-MIPS: "-m" "mipselelf_nacl"
-// CHECK-MIPS: "-static"
-// CHECK-MIPS: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}lib"
-// CHECK-MIPS: "-L{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}usr{{/|\\\\}}lib"
-// CHECK-MIPS: "-Lfoo{{/|\\\\}}lib{{/|\\\\}}mipsel-nacl"
-// CHECK-MIPS: "-lpnacl_legacy"
-// CHECK-MIPS-NOT: "-lpthread"
-
-// Check that even when the target arch is just "arm" (as will be the case when
-// it is inferred from the binary name) that we get the right ABI flags
-// RUN: %clang -### %s 2>&1 \
-// RUN: --target=arm-nacl \
-// RUN: | FileCheck --check-prefix=CHECK-ARM-NOV7 %s
-// CHECK-ARM-NOV7: "-triple" "armv7-unknown-nacl-gnueabihf"
-// CHECK-ARM-NOV7: "-target-abi" "aapcs-linux"
-// CHECK-ARM-NOV7: "-mfloat-abi" "hard"
-// CHECK-ARM-NOV7: as{{(.exe)?}}"
-// CHECK-ARM-NOV7: "-mfloat-abi=hard"
-
-// Test clang c++ include dirs and link line when using clang++
-
-// RUN: %clangxx -### %s \
-// RUN: --target=armv7a-unknown-nacl-gnueabihf -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-ARM-CXX %s
-// CHECK-ARM-CXX: "-cc1"
-// CHECK-ARM-CXX: "-resource-dir" "foo"
-// CHECK-ARM-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-ARM-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-ARM-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-ARM-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}arm-nacl{{/|\\\\}}include"
-// CHECK-ARM-CXX: "-lpthread"
-
-// RUN: %clangxx -### %s \
-// RUN: --target=i686-unknown-nacl -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-I686-CXX %s
-// CHECK-I686-CXX: "-cc1"
-// CHECK-I686-CXX: "-resource-dir" "foo"
-// CHECK-I686-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-I686-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-I686-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}i686-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-I686-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-I686-CXX: "-lpthread"
-
-// RUN: %clangxx -### %s \
-// RUN: --target=x86_64-unknown-nacl -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-x86_64-CXX %s
-// CHECK-x86_64-CXX: "-cc1"
-// CHECK-x86_64-CXX: "-resource-dir" "foo"
-// CHECK-x86_64-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-x86_64-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-x86_64-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-x86_64-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}x86_64-nacl{{/|\\\\}}include"
-// CHECK-x86_64-CXX: "-lpthread"
-
-// RUN: %clangxx -### %s \
-// RUN: --target=mipsel-unknown-nacl -resource-dir foo 2>&1 \
-// RUN: | FileCheck --check-prefix=CHECK-MIPS-CXX %s
-// CHECK-MIPS-CXX: "-cc1"
-// CHECK-MIPS-CXX: "-resource-dir" "foo"
-// CHECK-MIPS-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}include{{/|\\\\}}c++{{/|\\\\}}v1"
-// CHECK-MIPS-CXX: "-internal-isystem" "foo{{/|\\\\}}include"
-// CHECK-MIPS-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}usr{{/|\\\\}}include"
-// CHECK-MIPS-CXX: "-internal-isystem" "{{.*}}{{/|\\\\}}..{{/|\\\\}}mipsel-nacl{{/|\\\\}}include"
-// CHECK-MIPS-CXX: "-lnacl"
-// CHECK-MIPS-CXX: "-lpthread"
diff --git a/clang/test/Driver/unsupported-target-arch.c b/clang/test/Driver/unsupported-target-arch.c
index c0ec235439bca..426f646db50b0 100644
--- a/clang/test/Driver/unsupported-target-arch.c
+++ b/clang/test/Driver/unsupported-target-arch.c
@@ -20,10 +20,6 @@
// RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-NOARCH-NETBSD %s
// CHECK-NOARCH-NETBSD: error: unknown target triple 'noarch-unknown-netbsd'{{$}}
//
-// RUN: not %clang --target=noarch-unknown-nacl -o %t.o %s 2> %t.err
-// RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-NOARCH-NACL %s
-// CHECK-NOARCH-NACL: error: the target architecture 'noarch' is not supported by the target 'Native Client'
-
// RUN: not %clang --target=noarch-unknown-windows-gnu -o %t.o %s 2> %t.err
// RUN: FileCheck --input-file=%t.err --check-prefix=CHECK-NOARCH-MINGW %s
// CHECK-NOARCH-MINGW: error: unknown target triple 'noarch-unknown-windows-gnu'
diff --git a/clang/test/Driver/x86_64-nacl-defines.cpp b/clang/test/Driver/x86_64-nacl-defines.cpp
deleted file mode 100644
index 1b29fc7922419..0000000000000
--- a/clang/test/Driver/x86_64-nacl-defines.cpp
+++ /dev/null
@@ -1,45 +0,0 @@
-// RUN: %clang --target=x86_64-unknown-nacl -### %s -c -o %t.o 2>&1 | FileCheck %s -check-prefix=ECHO
-// RUN: %clang -target x86_64-unknown-nacl %s -emit-llvm -S -c -o - | FileCheck %s
-// RUN: %clang -target x86_64-unknown-nacl %s -emit-llvm -S -c -pthread -o - | FileCheck %s -check-prefix=THREADS
-
-// ECHO: {{.*}} "-cc1" {{.*}}x86_64-nacl-defines.c
-
-// Check platform defines
-
-// CHECK: __LITTLE_ENDIAN__defined
-#ifdef __LITTLE_ENDIAN__
-void __LITTLE_ENDIAN__defined() {}
-#endif
-
-// CHECK: __native_client__defined
-#ifdef __native_client__
-void __native_client__defined() {}
-#endif
-
-// CHECK: __x86_64__defined
-#ifdef __x86_64__
-void __x86_64__defined() {}
-#endif
-
-// CHECK: unixdefined
-#ifdef unix
-void unixdefined() {}
-#endif
-
-// CHECK: __ELF__defined
-#ifdef __ELF__
-void __ELF__defined() {}
-#endif
-
-// CHECK: _GNU_SOURCEdefined
-#ifdef _GNU_SOURCE
-void _GNU_SOURCEdefined() {}
-#endif
-
-// THREADS: _REENTRANTdefined
-// CHECK: _REENTRANTundefined
-#ifdef _REENTRANT
-void _REENTRANTdefined() {}
-#else
-void _REENTRANTundefined() {}
-#endif
diff --git a/clang/test/Frontend/x86_64-nacl-types.cpp b/clang/test/Frontend/x86_64-nacl-types.cpp
deleted file mode 100644
index ca200147f4013..0000000000000
--- a/clang/test/Frontend/x86_64-nacl-types.cpp
+++ /dev/null
@@ -1,37 +0,0 @@
-// RUN: %clang_cc1 -triple x86_64-unknown-nacl -std=c++11 -verify %s
-// expected-no-diagnostics
-
-#include <stddef.h>
-#include <stdarg.h>
-
-static_assert(alignof(char) == 1, "alignof char is wrong");
-
-static_assert(sizeof(short) == 2, "sizeof short is wrong");
-static_assert(alignof(short) == 2, "alignof short is wrong");
-
-static_assert(sizeof(int) == 4, "sizeof int is wrong");
-static_assert(alignof(int) == 4, "alignof int is wrong");
-
-static_assert(sizeof(long) == 4, "sizeof long is wrong");
-static_assert(alignof(long) == 4, "alignof long is wrong");
-
-static_assert(sizeof(long long) == 8, "sizeof long long is wrong wrong");
-static_assert(alignof(long long) == 8, "alignof long long is wrong wrong");
-
-static_assert(sizeof(void*) == 4, "sizeof void * is wrong");
-static_assert(alignof(void*) == 4, "alignof void * is wrong");
-
-static_assert(sizeof(float) == 4, "sizeof float is wrong");
-static_assert(alignof(float) == 4, "alignof float is wrong");
-
-static_assert(sizeof(double) == 8, "sizeof double is wrong");
-static_assert(alignof(double) == 8, "alignof double is wrong");
-
-static_assert(sizeof(long double) == 8, "sizeof long double is wrong");
-static_assert(alignof(long double) == 8, "alignof long double is wrong");
-
-static_assert(sizeof(va_list) == 16, "sizeof va_list is wrong");
-static_assert(alignof(va_list) == 4, "alignof va_list is wrong");
-
-static_assert(sizeof(size_t) == 4, "sizeof size_t is wrong");
-static_assert(alignof(size_t) == 4, "alignof size_t is wrong");
diff --git a/clang/test/Preprocessor/predefined-macros-no-warnings.c b/clang/test/Preprocessor/predefined-macros-no-warnings.c
index 4e3e29ccfa8a8..95108f9996ab3 100644
--- a/clang/test/Preprocessor/predefined-macros-no-warnings.c
+++ b/clang/test/Preprocessor/predefined-macros-no-warnings.c
@@ -33,7 +33,6 @@
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-netbsd
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-openbsd
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-rtems
-// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-nacl
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-win32-cygnus
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-win32-gnu
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple arm-win32-itanium
@@ -59,7 +58,6 @@
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mipsel-rtems
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mipsel-freebsd
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mipsel-netbsd
-// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mipsel-nacl
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mips64
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mips64-linux
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple mips64-rtems
@@ -145,7 +143,6 @@
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple i686-win32-msvc
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple i686-haiku
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple i686-rtems
-// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple i686-nacl
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple i686-elfiamcu
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple i686-hurd
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64
@@ -164,7 +161,6 @@
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64-win32gnu
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64-win32msvc
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64-haiku
-// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64-nacl
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64-ps4
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple x86_64-ps5
// RUN: %clang_cc1 %s -Eonly -Wsystem-headers -Werror -triple spir
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h b/llvm/include/llvm/BinaryFormat/ELF.h
index 1f3cea4bd1ae6..256f05015ea5b 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -1959,7 +1959,6 @@ enum {
GNU_ABI_TAG_FREEBSD = 3,
GNU_ABI_TAG_NETBSD = 4,
GNU_ABI_TAG_SYLLABLE = 5,
- GNU_ABI_TAG_NACL = 6,
};
constexpr const char *ELF_NOTE_GNU = "GNU";
diff --git a/llvm/include/llvm/BinaryFormat/MinidumpConstants.def b/llvm/include/llvm/BinaryFormat/MinidumpConstants.def
index 722a70ff67a9d..a04bb4c25f44e 100644
--- a/llvm/include/llvm/BinaryFormat/MinidumpConstants.def
+++ b/llvm/include/llvm/BinaryFormat/MinidumpConstants.def
@@ -118,7 +118,6 @@ HANDLE_MDMP_PLATFORM(0x8201, Linux) // Linux
HANDLE_MDMP_PLATFORM(0x8202, Solaris) // Solaris
HANDLE_MDMP_PLATFORM(0x8203, Android) // Android
HANDLE_MDMP_PLATFORM(0x8204, PS3) // PS3
-HANDLE_MDMP_PLATFORM(0x8205, NaCl) // Native Client (NaCl)
HANDLE_MDMP_PLATFORM(0x8206, OpenHOS) // OpenHarmony OS
HANDLE_MDMP_PROTECT(0x01, NoAccess, PAGE_NO_ACCESS)
diff --git a/llvm/include/llvm/CodeGen/AtomicExpandUtils.h b/llvm/include/llvm/CodeGen/AtomicExpandUtils.h
index feb05de20b457..3a7eda68cdc27 100644
--- a/llvm/include/llvm/CodeGen/AtomicExpandUtils.h
+++ b/llvm/include/llvm/CodeGen/AtomicExpandUtils.h
@@ -35,8 +35,7 @@ using CreateCmpXchgInstFun = function_ref<void(
/// instructions directly into a platform specific intrinsics (because, say,
/// those intrinsics don't exist). If such a pass is able to expand cmpxchg
/// instructions directly however, then, with this function, it could avoid two
-/// extra module passes (avoiding passes by `-atomic-expand` and itself). A
-/// specific example would be PNaCl's `RewriteAtomics` pass.
+/// extra module passes (avoiding passes by `-atomic-expand` and itself).
///
/// Given: atomicrmw some_op iN* %addr, iN %incr ordering
///
diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h
index fb6bbc0163701..b74743512ea74 100644
--- a/llvm/include/llvm/TargetParser/Triple.h
+++ b/llvm/include/llvm/TargetParser/Triple.h
@@ -216,7 +216,6 @@ class Triple {
ZOS,
Haiku,
RTEMS,
- NaCl, // Native Client
AIX,
CUDA, // NVIDIA CUDA
NVCL, // NVIDIA OpenCL
@@ -706,11 +705,6 @@ class Triple {
isWindowsItaniumEnvironment();
}
- /// Tests whether the OS is NaCl (Native Client)
- bool isOSNaCl() const {
- return getOS() == Triple::NaCl;
- }
-
/// Tests whether the OS is Linux.
bool isOSLinux() const {
return getOS() == Triple::Linux;
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index db8e467eedf64..57b41c6e45e37 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -2008,12 +2008,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
}
break;
}
- case ARM::TRAPNaCl: {
- uint32_t Val = 0xe7fedef0UL;
- OutStreamer->AddComment("trap");
- ATS.emitInst(Val);
- return;
- }
case ARM::tTRAP: {
// Non-Darwin binutils don't yet support the "trap" mnemonic.
// FIXME: Remove this special case when they do.
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp
index 765c65c5fcb24..16fa3fa3eebbe 100644
--- a/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -2635,12 +2635,8 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
return SelectCall(&I, "memset");
}
case Intrinsic::trap: {
- unsigned Opcode;
- if (Subtarget->isThumb())
- Opcode = ARM::tTRAP;
- else
- Opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opcode));
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+ TII.get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
return true;
}
}
diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
index bb437698296ce..9b1fa5d7b99d8 100644
--- a/llvm/lib/Target/ARM/ARMFeatures.td
+++ b/llvm/lib/Target/ARM/ARMFeatures.td
@@ -451,12 +451,6 @@ def FeatureVirtualization : SubtargetFeature<"virtualization",
"Supports Virtualization extension",
[FeatureHWDivThumb, FeatureHWDivARM]>;
-// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
-// See ARMInstrInfo.td for details.
-// True if NaCl TRAP instruction is generated instead of the regular TRAP.
-def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
- "NaCl trap">;
-
// True if the subtarget disallows unaligned memory
// accesses for some types. For details, see
// ARMTargetLowering::allowsMisalignedMemoryAccesses().
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 475f53fc03399..4998e891966f1 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -1748,9 +1748,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
RetOpcode == ARM::TCRETURNrinotr12);
isInterrupt =
RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
- isTrap =
- RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
- RetOpcode == ARM::tTRAP;
+ isTrap = RetOpcode == ARM::TRAP || RetOpcode == ARM::tTRAP;
isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index d2f9ec982ae01..2382caa456e54 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -11063,13 +11063,8 @@ void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
DispatchBB->setIsEHPad();
MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
- unsigned trap_opcode;
- if (Subtarget->isThumb())
- trap_opcode = ARM::tTRAP;
- else
- trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
- BuildMI(TrapBB, dl, TII->get(trap_opcode));
+ BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
DispatchBB->addSuccessor(TrapBB);
MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 2a3a4e91eee4c..c39a0956523ef 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2390,29 +2390,13 @@ def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary,
/*
* A5.4 Permanently UNDEFINED instructions.
*
- * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
- * Other UDF encodings generate SIGILL.
+ * Targets use UDF #65006, for which the OS will generate SIGTRAP.
*
- * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
- * Encoding A1:
- * 1110 0111 1111 iiii iiii iiii 1111 iiii
- * Encoding T1:
- * 1101 1110 iiii iiii
- * It uses the following encoding:
- * 1110 0111 1111 1110 1101 1110 1111 0000
- * - In ARM: UDF #60896;
- * - In Thumb: UDF #254 followed by a branch-to-self.
*/
let isTrap = 1 in
-def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
- "trap", [(trap)]>,
- Requires<[IsARM,UseNaClTrap]> {
- let Inst = 0xe7fedef0;
-}
-let isTrap = 1 in
def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
"trap", [(trap)]>,
- Requires<[IsARM,DontUseNaClTrap]> {
+ Requires<[IsARM]> {
let Inst = 0xe7ffdefe;
}
diff --git a/llvm/lib/Target/ARM/ARMPredicates.td b/llvm/lib/Target/ARM/ARMPredicates.td
index ddc5ad8754eee..c638e96a355d1 100644
--- a/llvm/lib/Target/ARM/ARMPredicates.td
+++ b/llvm/lib/Target/ARM/ARMPredicates.td
@@ -167,16 +167,12 @@ def IsARM : Predicate<"!Subtarget->isThumb()">,
AssemblerPredicate<(all_of (not ModeThumb)), "arm-mode">;
def IsMachO : Predicate<"Subtarget->isTargetMachO()">;
def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">;
-def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">;
def IsReadTPTPIDRURW : Predicate<"Subtarget->isReadTPTPIDRURW()">;
def IsReadTPTPIDRURO : Predicate<"Subtarget->isReadTPTPIDRURO()">;
def IsReadTPTPIDRPRW : Predicate<"Subtarget->isReadTPTPIDRPRW()">;
def IsReadTPSoft : Predicate<"Subtarget->isReadTPSoft()">;
-def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
- AssemblerPredicate<(all_of FeatureNaClTrap), "NaCl">;
-def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
def UseNegativeImmediates :
Predicate<"false">,
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 893084785e6f0..6489f57940247 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -203,7 +203,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (isAAPCS_ABI())
stackAlignment = Align(8);
- if (isTargetNaCl() || isAAPCS16_ABI())
+ if (isAAPCS16_ABI())
stackAlignment = Align(16);
// FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
@@ -440,10 +440,9 @@ bool ARMSubtarget::useFastISel() const {
if (!hasV6Ops())
return false;
- // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
- return TM.Options.EnableFastISel &&
- ((isTargetMachO() && !isThumb1Only()) ||
- (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
+ // Thumb2 support on iOS; ARM support on iOS and Linux.
+ return TM.Options.EnableFastISel && ((isTargetMachO() && !isThumb1Only()) ||
+ (isTargetLinux() && !isThumb()));
}
unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 7329d3f2055f0..35b7c3b60e1a7 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -340,7 +340,6 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
- bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index a0d56704305a3..9b3d5b91d8c0b 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -183,9 +183,8 @@ static std::string computeDataLayout(const Triple &TT, StringRef CPU,
// Integer registers are 32 bits.
Ret += "-n32";
- // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
- // aligned everywhere else.
- if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
+ // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
+ if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
Ret += "-S128";
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
Ret += "-S64";
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
index 103d2ed1c6281..599e64296ddf4 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h
@@ -91,9 +91,9 @@ class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
ARM::FeatureAvoidMOVsShOp, ARM::FeatureHasRetAddrStack,
ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
- ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
- ARM::FeatureLongCalls, ARM::FeatureExecuteOnly, ARM::FeatureReserveR9,
- ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
+ ARM::FeatureAClass, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
+ ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
+ ARM::FeatureNoNegativeImmediates
};
const ARMSubtarget *getST() const { return ST; }
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index c756bff3b501a..c4927829b5098 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -151,12 +151,6 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
ARMArchFeature += "+thumb-mode,+v4t";
}
- if (TT.isOSNaCl()) {
- if (!ARMArchFeature.empty())
- ARMArchFeature += ",";
- ARMArchFeature += "+nacl-trap";
- }
-
if (TT.isOSWindows()) {
if (!ARMArchFeature.empty())
ARMArchFeature += ",";
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
index d3f16e5042c3a..749f6d0aabe02 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/MCTargetDesc/CMakeLists.txt
@@ -9,7 +9,6 @@ add_llvm_component_library(LLVMMipsDesc
MipsMCCodeEmitter.cpp
MipsMCExpr.cpp
MipsMCTargetDesc.cpp
- MipsNaClELFStreamer.cpp
MipsOptionRecord.cpp
MipsTargetStreamer.cpp
MipsWinCOFFObjectWriter.cpp
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
deleted file mode 100644
index 94b2f412c8cdb..0000000000000
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h
+++ /dev/null
@@ -1,31 +0,0 @@
-//===-- MipsMCNaCl.h - NaCl-related declarations --------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
-#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H
-
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/Support/Alignment.h"
-
-namespace llvm {
-
-// NaCl MIPS sandbox's instruction bundle size.
-static const Align MIPS_NACL_BUNDLE_ALIGN = Align(16);
-
-bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
- bool *IsStore = nullptr);
-bool baseRegNeedsLoadStoreMask(MCRegister Reg);
-
-// This function creates an MCELFStreamer for Mips NaCl.
-MCELFStreamer *
-createMipsNaClELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
- std::unique_ptr<MCObjectWriter> OW,
- std::unique_ptr<MCCodeEmitter> Emitter);
-}
-
-#endif
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index add36d87b9eff..09e4a7188a704 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -16,7 +16,6 @@
#include "MipsELFStreamer.h"
#include "MipsInstPrinter.h"
#include "MipsMCAsmInfo.h"
-#include "MipsMCNaCl.h"
#include "MipsTargetStreamer.h"
#include "TargetInfo/MipsTargetInfo.h"
#include "llvm/DebugInfo/CodeView/CodeView.h"
@@ -198,12 +197,8 @@ static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter) {
MCStreamer *S;
- if (!T.isOSNaCl())
- S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
- std::move(Emitter));
- else
- S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW),
- std::move(Emitter));
+ S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
+ std::move(Emitter));
return S;
}
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
deleted file mode 100644
index 3410726c8e553..0000000000000
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
+++ /dev/null
@@ -1,274 +0,0 @@
-//===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements MCELFStreamer for Mips NaCl. It emits .o object files
-// as required by NaCl's SFI sandbox. It inserts address-masking instructions
-// before dangerous control-flow and memory access instructions. It inserts
-// address-masking instructions after instructions that change the stack
-// pointer. It ensures that the mask and the dangerous instruction are always
-// emitted in the same bundle. It aligns call + branch delay to the bundle end,
-// so that return address is always aligned to the start of next bundle.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MipsELFStreamer.h"
-#include "MipsMCNaCl.h"
-#include "llvm/MC/MCAsmBackend.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCCodeEmitter.h"
-#include "llvm/MC/MCELFStreamer.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/Support/ErrorHandling.h"
-#include <cassert>
-
-using namespace llvm;
-
-#define DEBUG_TYPE "mips-mc-nacl"
-
-namespace {
-
-const unsigned IndirectBranchMaskReg = Mips::T6;
-const unsigned LoadStoreStackMaskReg = Mips::T7;
-
-/// Extend the generic MCELFStreamer class so that it can mask dangerous
-/// instructions.
-
-class MipsNaClELFStreamer : public MipsELFStreamer {
-public:
- MipsNaClELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
- std::unique_ptr<MCObjectWriter> OW,
- std::unique_ptr<MCCodeEmitter> Emitter)
- : MipsELFStreamer(Context, std::move(TAB), std::move(OW),
- std::move(Emitter)) {}
-
- ~MipsNaClELFStreamer() override = default;
-
-private:
- // Whether we started the sandboxing sequence for calls. Calls are bundled
- // with branch delays and aligned to the bundle end.
- bool PendingCall = false;
-
- bool isIndirectJump(const MCInst &MI) {
- if (MI.getOpcode() == Mips::JALR) {
- // MIPS32r6/MIPS64r6 doesn't have a JR instruction and uses JALR instead.
- // JALR is an indirect branch if the link register is $0.
- assert(MI.getOperand(0).isReg());
- return MI.getOperand(0).getReg() == Mips::ZERO;
- }
- return MI.getOpcode() == Mips::JR;
- }
-
- bool isStackPointerFirstOperand(const MCInst &MI) {
- return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
- && MI.getOperand(0).getReg() == Mips::SP);
- }
-
- bool isCall(const MCInst &MI, bool *IsIndirectCall) {
- unsigned Opcode = MI.getOpcode();
-
- *IsIndirectCall = false;
-
- switch (Opcode) {
- default:
- return false;
-
- case Mips::JAL:
- case Mips::BAL:
- case Mips::BAL_BR:
- case Mips::BLTZAL:
- case Mips::BGEZAL:
- return true;
-
- case Mips::JALR:
- // JALR is only a call if the link register is not $0. Otherwise it's an
- // indirect branch.
- assert(MI.getOperand(0).isReg());
- if (MI.getOperand(0).getReg() == Mips::ZERO)
- return false;
-
- *IsIndirectCall = true;
- return true;
- }
- }
-
- void emitMask(MCRegister AddrReg, unsigned MaskReg,
- const MCSubtargetInfo &STI) {
- MCInst MaskInst;
- MaskInst.setOpcode(Mips::AND);
- MaskInst.addOperand(MCOperand::createReg(AddrReg));
- MaskInst.addOperand(MCOperand::createReg(AddrReg));
- MaskInst.addOperand(MCOperand::createReg(MaskReg));
- MipsELFStreamer::emitInstruction(MaskInst, STI);
- }
-
- // Sandbox indirect branch or return instruction by inserting mask operation
- // before it.
- void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) {
- MCRegister AddrReg = MI.getOperand(0).getReg();
-
- emitBundleLock(false);
- emitMask(AddrReg, IndirectBranchMaskReg, STI);
- MipsELFStreamer::emitInstruction(MI, STI);
- emitBundleUnlock();
- }
-
- // Sandbox memory access or SP change. Insert mask operation before and/or
- // after the instruction.
- void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
- const MCSubtargetInfo &STI, bool MaskBefore,
- bool MaskAfter) {
- emitBundleLock(false);
- if (MaskBefore) {
- // Sandbox memory access.
- MCRegister BaseReg = MI.getOperand(AddrIdx).getReg();
- emitMask(BaseReg, LoadStoreStackMaskReg, STI);
- }
- MipsELFStreamer::emitInstruction(MI, STI);
- if (MaskAfter) {
- // Sandbox SP change.
- MCRegister SPReg = MI.getOperand(0).getReg();
- assert((Mips::SP == SPReg) && "Unexpected stack-pointer register.");
- emitMask(SPReg, LoadStoreStackMaskReg, STI);
- }
- emitBundleUnlock();
- }
-
-public:
- /// This function is the one used to emit instruction data into the ELF
- /// streamer. We override it to mask dangerous instructions.
- void emitInstruction(const MCInst &Inst,
- const MCSubtargetInfo &STI) override {
- // Sandbox indirect jumps.
- if (isIndirectJump(Inst)) {
- if (PendingCall)
- report_fatal_error("Dangerous instruction in branch delay slot!");
- sandboxIndirectJump(Inst, STI);
- return;
- }
-
- // Sandbox loads, stores and SP changes.
- unsigned AddrIdx = 0;
- bool IsStore = false;
- bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
- &IsStore);
- bool IsSPFirstOperand = isStackPointerFirstOperand(Inst);
- if (IsMemAccess || IsSPFirstOperand) {
- bool MaskBefore = (IsMemAccess
- && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
- .getReg()));
- bool MaskAfter = IsSPFirstOperand && !IsStore;
- if (MaskBefore || MaskAfter) {
- if (PendingCall)
- report_fatal_error("Dangerous instruction in branch delay slot!");
- sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
- return;
- }
- // fallthrough
- }
-
- // Sandbox calls by aligning call and branch delay to the bundle end.
- // For indirect calls, emit the mask before the call.
- bool IsIndirectCall;
- if (isCall(Inst, &IsIndirectCall)) {
- if (PendingCall)
- report_fatal_error("Dangerous instruction in branch delay slot!");
-
- // Start the sandboxing sequence by emitting call.
- emitBundleLock(true);
- if (IsIndirectCall) {
- MCRegister TargetReg = Inst.getOperand(1).getReg();
- emitMask(TargetReg, IndirectBranchMaskReg, STI);
- }
- MipsELFStreamer::emitInstruction(Inst, STI);
- PendingCall = true;
- return;
- }
- if (PendingCall) {
- // Finish the sandboxing sequence by emitting branch delay.
- MipsELFStreamer::emitInstruction(Inst, STI);
- emitBundleUnlock();
- PendingCall = false;
- return;
- }
-
- // None of the sandboxing applies, just emit the instruction.
- MipsELFStreamer::emitInstruction(Inst, STI);
- }
-};
-
-} // end anonymous namespace
-
-namespace llvm {
-
-bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
- bool *IsStore) {
- if (IsStore)
- *IsStore = false;
-
- switch (Opcode) {
- default:
- return false;
-
- // Load instructions with base address register in position 1.
- case Mips::LB:
- case Mips::LBu:
- case Mips::LH:
- case Mips::LHu:
- case Mips::LW:
- case Mips::LWC1:
- case Mips::LDC1:
- case Mips::LL:
- case Mips::LL_R6:
- case Mips::LWL:
- case Mips::LWR:
- *AddrIdx = 1;
- return true;
-
- // Store instructions with base address register in position 1.
- case Mips::SB:
- case Mips::SH:
- case Mips::SW:
- case Mips::SWC1:
- case Mips::SDC1:
- case Mips::SWL:
- case Mips::SWR:
- *AddrIdx = 1;
- if (IsStore)
- *IsStore = true;
- return true;
-
- // Store instructions with base address register in position 2.
- case Mips::SC:
- case Mips::SC_R6:
- *AddrIdx = 2;
- if (IsStore)
- *IsStore = true;
- return true;
- }
-}
-
-bool baseRegNeedsLoadStoreMask(MCRegister Reg) {
- // The contents of SP and thread pointer register do not require masking.
- return Reg != Mips::SP && Reg != Mips::T8;
-}
-
-MCELFStreamer *
-createMipsNaClELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
- std::unique_ptr<MCObjectWriter> OW,
- std::unique_ptr<MCCodeEmitter> Emitter) {
- MipsNaClELFStreamer *S = new MipsNaClELFStreamer(
- Context, std::move(TAB), std::move(OW), std::move(Emitter));
-
- // Set bundle-alignment as required by the NaCl ABI for the target.
- S->emitBundleAlignMode(MIPS_NACL_BUNDLE_ALIGN);
-
- return S;
-}
-
-} // end namespace llvm
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index b411056b332f7..249108a691e4d 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -15,7 +15,6 @@
#include "MCTargetDesc/MipsABIInfo.h"
#include "MCTargetDesc/MipsBaseInfo.h"
#include "MCTargetDesc/MipsInstPrinter.h"
-#include "MCTargetDesc/MipsMCNaCl.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "MCTargetDesc/MipsTargetStreamer.h"
#include "Mips.h"
@@ -85,10 +84,6 @@ bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
StubsNeeded.insert(I);
MCP = MF.getConstantPool();
- // In NaCl, all indirect jump targets must be aligned to bundle size.
- if (Subtarget->isTargetNaCl())
- NaClAlignIndirectJumpTargets(MF);
-
AsmPrinter::runOnMachineFunction(MF);
emitXRayTable();
@@ -399,11 +394,6 @@ const char *MipsAsmPrinter::getCurrentABIString() const {
void MipsAsmPrinter::emitFunctionEntryLabel() {
MipsTargetStreamer &TS = getTargetStreamer();
- // NaCl sandboxing requires that indirect call instructions are masked.
- // This means that function entry points should be bundle-aligned.
- if (Subtarget->isTargetNaCl())
- emitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
-
if (Subtarget->inMicroMipsMode()) {
TS.emitDirectiveSetMicroMips();
TS.setUsesMicroMips();
@@ -1262,27 +1252,6 @@ void MipsAsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const {
AsmPrinter::emitDebugValue(Value, Size);
}
-// Align all targets of indirect branches on bundle size. Used only if target
-// is NaCl.
-void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
- // Align all blocks that are jumped to through jump table.
- if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
- const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
- for (const auto &I : JT) {
- const std::vector<MachineBasicBlock *> &MBBs = I.MBBs;
-
- for (MachineBasicBlock *MBB : MBBs)
- MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
- }
- }
-
- // If basic block address is taken, block can be target of indirect branch.
- for (auto &MBB : MF) {
- if (MBB.hasAddressTaken())
- MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
- }
-}
-
bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
return (Opcode == Mips::LONG_BRANCH_LUi
|| Opcode == Mips::LONG_BRANCH_LUi2Op
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h
index 060bba6ef65e0..12cd3d03b44eb 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.h
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h
@@ -112,8 +112,6 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter {
void EmitFPCallStub(const char *, const Mips16HardFloatInfo::FuncSignature *);
- void NaClAlignIndirectJumpTargets(MachineFunction &MF);
-
bool isLongBranchPseudo(int Opcode) const;
public:
diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
index eb7f3f8792bfb..56d535e5d3b60 100644
--- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
+++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp
@@ -74,7 +74,6 @@
#include "MCTargetDesc/MipsABIInfo.h"
#include "MCTargetDesc/MipsBaseInfo.h"
-#include "MCTargetDesc/MipsMCNaCl.h"
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "Mips.h"
#include "MipsInstrInfo.h"
@@ -520,27 +519,19 @@ void MipsBranchExpansion::expandToLongBranch(MBBInfo &I) {
BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
.addReg(Mips::SP)
.addImm(0);
- if (STI->isTargetNaCl())
- // Bundle-align the target of indirect branch JR.
- TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
- // In NaCl, modifying the sp is not allowed in branch delay slot.
// For MIPS32R6, we can skip using a delay slot branch.
bool hasDelaySlot = buildProperJumpMI(BalTgtMBB, Pos, DL);
- if (STI->isTargetNaCl() || !hasDelaySlot) {
+ if (!hasDelaySlot) {
BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
.addReg(Mips::SP)
.addImm(8);
}
if (hasDelaySlot) {
- if (STI->isTargetNaCl()) {
- TII->insertNop(*BalTgtMBB, Pos, DL);
- } else {
- BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
- .addReg(Mips::SP)
- .addImm(8);
- }
+ BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
+ .addReg(Mips::SP)
+ .addImm(8);
BalTgtMBB->rbegin()->bundleWithPred();
}
} else {
@@ -901,14 +892,6 @@ bool MipsBranchExpansion::handlePossibleLongBranch() {
(Br->isUnconditionalBranch() && IsPIC))) {
int64_t Offset = computeOffset(&*Br);
- if (STI->isTargetNaCl()) {
- // The offset calculation does not include sandboxing instructions
- // that will be added later in the MC layer. Since at this point we
- // don't know the exact amount of code that "sandboxing" will add, we
- // conservatively estimate that code will not grow more than 100%.
- Offset *= 2;
- }
-
if (ForceLongBranchFirstPass ||
!TII->isBranchOffsetInRange(Br->getOpcode(), Offset)) {
MBBInfos[I].Offset = Offset;
diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td
index 25384a3fe8de3..6aa15d1842809 100644
--- a/llvm/lib/Target/Mips/MipsCallingConv.td
+++ b/llvm/lib/Target/Mips/MipsCallingConv.td
@@ -267,15 +267,8 @@ def CC_Mips_FastCC : CallingConv<[
// Integer arguments are passed in integer registers. All scratch registers,
// except for AT, V0 and T9, are available to be used as argument registers.
- CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()",
- CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>,
-
- // In NaCl, T6, T7 and T8 are reserved and not available as argument
- // registers for fastcc. T6 contains the mask for sandboxing control flow
- // (indirect jumps and calls). T7 contains the mask for sandboxing memory
- // accesses (loads and stores). T8 contains the thread pointer.
- CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()",
- CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>,
+ CCIfType<[i32],
+ CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>,
// f32 arguments are passed in single-precision floating pointer registers.
CCIfType<[f32], CCIfSubtarget<"useOddSPReg()",
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 258010d331181..c7b1eedb69fdb 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -10,7 +10,6 @@
//
//===----------------------------------------------------------------------===//
-#include "MCTargetDesc/MipsMCNaCl.h"
#include "Mips.h"
#include "MipsInstrInfo.h"
#include "MipsSubtarget.h"
@@ -729,18 +728,6 @@ bool MipsDelaySlotFiller::searchRange(MachineBasicBlock &MBB, IterTy Begin,
continue;
const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
- if (STI.isTargetNaCl()) {
- // In NaCl, instructions that must be masked are forbidden in delay slots.
- // We only check for loads, stores and SP changes. Calls, returns and
- // branches are not checked because non-NaCl targets never put them in
- // delay slots.
- unsigned AddrIdx;
- if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
- baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
- CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
- continue;
- }
-
bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo();
unsigned Opcode = (*Slot).getOpcode();
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 14590ddacfcb7..4ca329d214981 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -622,15 +622,13 @@ let AdditionalPredicates = [NotInMicroMips] in {
// Indexed loads and stores.
// Base register + offset register addressing mode (indicated by "x" in the
-// instruction mnemonic) is disallowed under NaCl.
-let AdditionalPredicates = [IsNotNaCl] in {
- def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
- INSN_MIPS4_32R2_NOT_32R6_64R6;
- def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
- INSN_MIPS4_32R2_NOT_32R6_64R6;
-}
+// instruction mnemonic).
+def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
+ INSN_MIPS4_32R2_NOT_32R6_64R6;
+def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
+ INSN_MIPS4_32R2_NOT_32R6_64R6;
-let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
+let AdditionalPredicates = [NotInMicroMips] in {
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
@@ -646,14 +644,14 @@ let DecoderNamespace="MipsFP64" in {
// Load/store doubleword indexed unaligned.
// FIXME: This instruction should not be defined for FGR_32.
-let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in {
+let AdditionalPredicates = [NotInMicroMips] in {
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
}
-let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
+let AdditionalPredicates = [NotInMicroMips],
DecoderNamespace="MipsFP64" in {
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 557e6a2c72e27..11a481dc27cb2 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -236,7 +236,6 @@ def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
AssemblerPredicate<(all_of (not FeatureMicroMips))>;
def IsLE : Predicate<"Subtarget->isLittle()">;
def IsBE : Predicate<"!Subtarget->isLittle()">;
-def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def UseTCCInDIV : AssemblerPredicate<(all_of FeatureUseTCCInDIV)>;
def HasEVA : Predicate<"Subtarget->hasEVA()">,
AssemblerPredicate<(all_of FeatureEVA)>;
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index ae4b2377ad218..539288e8da592 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -162,13 +162,6 @@ getReservedRegs(const MachineFunction &MF) const {
for (MCPhysReg R : ReservedGPR32)
Reserved.set(R);
- // Reserve registers for the NaCl sandbox.
- if (Subtarget.isTargetNaCl()) {
- Reserved.set(Mips::T6); // Reserved for control flow mask.
- Reserved.set(Mips::T7); // Reserved for memory access mask.
- Reserved.set(Mips::T8); // Reserved for thread pointer.
- }
-
for (MCPhysReg R : ReservedGPR64)
Reserved.set(R);
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 15127b11d5cdd..0484c34df7381 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -356,7 +356,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
bool os16() const { return Os16; }
- bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
bool isXRaySupported() const override { return true; }
diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
index c202f7fa93db6..3dd9205a2b38e 100644
--- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp
+++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp
@@ -373,8 +373,7 @@ bool X86ExpandPseudo::expandMI(MachineBasicBlock &MBB,
case X86::EH_RETURN64: {
MachineOperand &DestAddr = MBBI->getOperand(0);
assert(DestAddr.isReg() && "Offset should be in register!");
- const bool Uses64BitFramePtr =
- STI->isTarget64BitLP64() || STI->isTargetNaCl64();
+ const bool Uses64BitFramePtr = STI->isTarget64BitLP64();
Register StackPtr = TRI->getStackRegister();
BuildMI(MBB, MBBI, DL,
TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index b7374558604ec..2ab760535f7ff 100644
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -54,8 +54,8 @@ X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
SlotSize = TRI->getSlotSize();
Is64Bit = STI.is64Bit();
IsLP64 = STI.isTarget64BitLP64();
- // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
- Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
+ // standard x86_64 uses 64-bit frame/stack pointers, x32 - 32-bit.
+ Uses64BitFramePtr = STI.isTarget64BitLP64();
StackPtr = TRI->getStackRegister();
}
@@ -2411,7 +2411,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
DebugLoc DL;
if (MBBI != MBB.end())
DL = MBBI->getDebugLoc();
- // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
+ // standard x86_64 uses 64-bit frame/stack pointers, x32 - 32-bit.
const bool Is64BitILP32 = STI.isTarget64BitILP32();
Register FramePtr = TRI->getFrameRegister(MF);
Register MachineFramePtr =
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index d322e70fc0c20..8de92823f1860 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -5415,10 +5415,6 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
}
case ISD::BRIND:
case X86ISD::NT_BRIND: {
- if (Subtarget->isTargetNaCl())
- // NaCl has its own pass where jmp %r32 are converted to jmp %r64. We
- // leave the instruction alone.
- break;
if (Subtarget->isTarget64BitILP32()) {
// Converts a 32-bit register to a 64-bit, zero-extended version of
// it. This is needed because x86-64 can do many things, but jmp %r32
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 72977923bac2b..c99a97dc719dc 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36372,8 +36372,7 @@ X86TargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
sizeVReg = MI.getOperand(1).getReg(),
- physSPReg =
- IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP;
+ physSPReg = IsLP64 ? X86::RSP : X86::ESP;
MachineFunction::iterator MBBIter = ++BB->getIterator();
@@ -36878,8 +36877,7 @@ X86TargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
// restoreMBB:
if (RegInfo->hasBasePointer(*MF)) {
- const bool Uses64BitFramePtr =
- Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
+ const bool Uses64BitFramePtr = Subtarget.isTarget64BitLP64();
X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
X86FI->setRestoreBasePointer(MF);
Register FramePtr = RegInfo->getFrameRegister(*MF);
@@ -37307,8 +37305,7 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
// Add a register mask with no preserved registers. This results in all
// registers being marked as clobbered.
if (RI.hasBasePointer(*MF)) {
- const bool FPIs64Bit =
- Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
+ const bool FPIs64Bit = Subtarget.isTarget64BitLP64();
X86MachineFunctionInfo *MFI = MF->getInfo<X86MachineFunctionInfo>();
MFI->setRestoreBasePointer(MF);
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index 5bdcf51be9dd8..6fd09f0dbaeac 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -214,8 +214,6 @@ def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||"
}
def IsPS : Predicate<"Subtarget->isTargetPS()">;
def NotPS : Predicate<"!Subtarget->isTargetPS()">;
-def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
-def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp
index b563f6ebce34e..540f67c703114 100644
--- a/llvm/lib/Target/X86/X86Subtarget.cpp
+++ b/llvm/lib/Target/X86/X86Subtarget.cpp
@@ -302,13 +302,12 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
report_fatal_error("64-bit code requested on a subtarget that doesn't "
"support it!");
- // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD, NaCl, and for all
+ // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD, and for all
// 64-bit targets. On Solaris (32-bit), stack alignment is 4 bytes
// following the i386 psABI, while on Illumos it is always 16 bytes.
if (StackAlignOverride)
stackAlignment = *StackAlignOverride;
- else if (isTargetDarwin() || isTargetLinux() || isTargetKFreeBSD() ||
- isTargetNaCl() || Is64Bit)
+ else if (isTargetDarwin() || isTargetLinux() || isTargetKFreeBSD() || Is64Bit)
stackAlignment = Align(16);
// Consume the vector width attribute or apply any target specific limit.
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index 8f2d326a69398..230280b4fb458 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -170,14 +170,10 @@ class X86Subtarget final : public X86GenSubtargetInfo {
#include "X86GenSubtargetInfo.inc"
/// Is this x86_64 with the ILP32 programming model (x32 ABI)?
- bool isTarget64BitILP32() const {
- return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
- }
+ bool isTarget64BitILP32() const { return Is64Bit && (TargetTriple.isX32()); }
/// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
- bool isTarget64BitLP64() const {
- return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
- }
+ bool isTarget64BitLP64() const { return Is64Bit && (!TargetTriple.isX32()); }
PICStyles::Style getPICStyle() const { return PICStyle; }
void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
@@ -299,9 +295,6 @@ class X86Subtarget final : public X86GenSubtargetInfo {
bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
- bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
- bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
- bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 4cecbbf27aa30..ca843b3022f22 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -128,7 +128,7 @@ static std::string computeDataLayout(const Triple &TT) {
Ret += DataLayout::getManglingComponent(TT);
// X86 and x32 have 32 bit pointers.
- if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
+ if (!TT.isArch64Bit() || TT.isX32())
Ret += "-p:32:32";
// Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
@@ -137,7 +137,7 @@ static std::string computeDataLayout(const Triple &TT) {
// Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
// 128 bit integers are not specified in the 32-bit ABIs but are used
// internally for lowering f128, so we match the alignment to that.
- if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
+ if (TT.isArch64Bit() || TT.isOSWindows())
Ret += "-i64:64-i128:128";
else if (TT.isOSIAMCU())
Ret += "-i64:32-f64:32";
@@ -145,7 +145,7 @@ static std::string computeDataLayout(const Triple &TT) {
Ret += "-i128:128-f64:32:64";
// Some ABIs align long double to 128 bits, others to 32.
- if (TT.isOSNaCl() || TT.isOSIAMCU())
+ if (TT.isOSIAMCU())
; // No f80
else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
Ret += "-f80:128";
diff --git a/llvm/lib/TargetParser/ARMTargetParser.cpp b/llvm/lib/TargetParser/ARMTargetParser.cpp
index 8f9753775c204..f18712bebfca2 100644
--- a/llvm/lib/TargetParser/ARMTargetParser.cpp
+++ b/llvm/lib/TargetParser/ARMTargetParser.cpp
@@ -631,7 +631,6 @@ StringRef ARM::getARMCPUForArch(const llvm::Triple &Triple, StringRef MArch) {
default:
return "strongarm";
}
- case llvm::Triple::NaCl:
case llvm::Triple::OpenBSD:
return "cortex-a8";
default:
diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp
index e9e6f130f757c..46a6b7b37aaef 100644
--- a/llvm/lib/TargetParser/Triple.cpp
+++ b/llvm/lib/TargetParser/Triple.cpp
@@ -301,7 +301,6 @@ StringRef Triple::getOSTypeName(OSType Kind) {
case MacOSX: return "macosx";
case Mesa3D: return "mesa3d";
case NVCL: return "nvcl";
- case NaCl: return "nacl";
case NetBSD: return "netbsd";
case OpenBSD: return "openbsd";
case PS4: return "ps4";
@@ -687,7 +686,6 @@ static Triple::OSType parseOS(StringRef OSName) {
.StartsWith("zos", Triple::ZOS)
.StartsWith("haiku", Triple::Haiku)
.StartsWith("rtems", Triple::RTEMS)
- .StartsWith("nacl", Triple::NaCl)
.StartsWith("aix", Triple::AIX)
.StartsWith("cuda", Triple::CUDA)
.StartsWith("nvcl", Triple::NVCL)
diff --git a/llvm/test/CodeGen/ARM/fast-isel-align.ll b/llvm/test/CodeGen/ARM/fast-isel-align.ll
index e7741155e6bf1..8adbc3039d4e1 100644
--- a/llvm/test/CodeGen/ARM/fast-isel-align.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel-align.ll
@@ -8,9 +8,6 @@
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
-; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM
-; RUN: llc < %s -O0 -mattr=+strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
-
; RUN: llc < %s -O0 -mattr=+strict-align -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -mattr=+strict-align -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM
diff --git a/llvm/test/CodeGen/ARM/struct_byval.ll b/llvm/test/CodeGen/ARM/struct_byval.ll
index 2bc4f9c816d53..f8059d08881ab 100644
--- a/llvm/test/CodeGen/ARM/struct_byval.ll
+++ b/llvm/test/CodeGen/ARM/struct_byval.ll
@@ -1,6 +1,5 @@
; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s
-; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL
; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT
; NOMOVT-NOT: movt
@@ -28,14 +27,6 @@ entry:
; CHECK: sub
; CHECK: str
; CHECK: bne
-; NACL-LABEL: g:
-; Ensure that use movw instead of constpool for the loop trip count. But don't
-; match the __stack_chk_guard movw
-; NACL: movw {{r[0-9]+|lr}}, #
-; NACL: ldr
-; NACL: sub
-; NACL: str
-; NACL: bne
%st = alloca %struct.LargeStruct, align 4
%call = call i32 @e2(ptr byval(%struct.LargeStruct) %st)
ret i32 0
@@ -49,11 +40,6 @@ entry:
; CHECK: sub
; CHECK: vst1
; CHECK: bne
-; NACL: movw {{r[0-9]+|lr}}, #
-; NACL: vld1
-; NACL: sub
-; NACL: vst1
-; NACL: bne
%st = alloca %struct.LargeStruct, align 16
%call = call i32 @e3(ptr byval(%struct.LargeStruct) align 16 %st)
ret i32 0
diff --git a/llvm/test/CodeGen/ARM/trap.ll b/llvm/test/CodeGen/ARM/trap.ll
index a5d2b2081f28f..88b69a4ed7b89 100644
--- a/llvm/test/CodeGen/ARM/trap.ll
+++ b/llvm/test/CodeGen/ARM/trap.ll
@@ -4,17 +4,9 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN
; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC
; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap -O0 | FileCheck %s -check-prefix=FUNC
-; RUN: llc < %s -mtriple=armv7 -mattr=+nacl-trap | FileCheck %s -check-prefix=NACL
; RUN: llc < %s -mtriple=armv7 | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=thumbv7 | FileCheck %s -check-prefix=THUMB
-; RUN: llc -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
-; RUN: | llvm-objdump -d --triple=armv7 --mattr=+nacl-trap - \
-; RUN: | FileCheck %s -check-prefix=ENCODING-NACL
-; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \
-; RUN: | llvm-objdump -d --triple=armv7 --mattr=+nacl-trap - \
-; RUN: | FileCheck %s -check-prefix=ENCODING-NACL
-
; RUN: llc -mtriple=armv7 -filetype=obj %s -o - \
; RUN: | llvm-objdump -d --triple=armv7 - \
; RUN: | FileCheck %s -check-prefix=ENCODING-ARM
@@ -46,10 +38,6 @@ entry:
; FUNC: bl __trap
; FUNC-NEXT: add sp, sp, #4
-; NACL-LABEL: t:
-; NACL: .inst 0xe7fedef0
-; NACL-NEXT: add sp, sp, #4
-
; ARM-LABEL: t:
; ARM: .inst 0xe7ffdefe
; ARM-NEXT: add sp, sp, #4
@@ -58,8 +46,6 @@ entry:
; THUMB: .inst.n 0xdefe
; THUMB-NEXT: add sp, #4
-; ENCODING-NACL: e7fedef0 trap
-
; ENCODING-ARM: e7ffdefe trap
; ENCODING-THUMB: defe trap
@@ -82,10 +68,6 @@ entry:
; FUNC: bl __trap
; FUNC-NEXT: add sp, sp, #4
-; NACL-LABEL: t2:
-; NACL: bkpt #0
-; NACL-NEXT: add sp, sp, #4
-
; ARM-LABEL: t2:
; ARM: bkpt #0
; ARM-NEXT: add sp, sp, #4
@@ -94,8 +76,6 @@ entry:
; THUMB: bkpt #0
; THUMB-NEXT: add sp, #4
-; ENCODING-NACL: e1200070 bkpt #0
-
; ENCODING-ARM: e1200070 bkpt #0
; ENCODING-THUMB: be00 bkpt #0
diff --git a/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll b/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
deleted file mode 100644
index 1dda1fed366b0..0000000000000
--- a/llvm/test/CodeGen/ARM/varargs-spill-stack-align-nacl.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc < %s -mtriple=arm-nacl-gnueabi | FileCheck %s
-
-declare void @llvm.va_start(ptr)
-declare void @external_func(ptr)
-
- at va_list = external global ptr
-
-; On ARM, varargs arguments are passed in r0-r3 with the rest on the
-; stack. A varargs function must therefore spill rN-r3 just below the
-; function's initial stack pointer.
-;
-; This test checks for a bug in which a gap was left between the spill
-; area and varargs arguments on the stack when using 16 byte stack
-; alignment.
-
-define void @varargs_func(i32 %arg1, ...) {
- call void @llvm.va_start(ptr @va_list)
- call void @external_func(ptr @va_list)
- ret void
-}
-; CHECK-LABEL: varargs_func:
-; Reserve space for the varargs save area. This currently reserves
-; more than enough (16 bytes rather than the 12 bytes needed).
-; CHECK: sub sp, sp, #12
-; CHECK: push {r11, lr}
-; Align the stack pointer to a multiple of 16.
-; CHECK: sub sp, sp, #12
-; Calculate the address of the varargs save area and save varargs
-; arguments into it.
-; CHECK-NEXT: add r0, sp, #20
-; CHECK-NEXT: stm r0, {r1, r2, r3}
diff --git a/llvm/test/CodeGen/Mips/fastcc.ll b/llvm/test/CodeGen/Mips/fastcc.ll
index e6d12664d83f4..4dbadbb24ea86 100644
--- a/llvm/test/CodeGen/Mips/fastcc.ll
+++ b/llvm/test/CodeGen/Mips/fastcc.ll
@@ -1,6 +1,4 @@
; RUN: llc < %s -mtriple=mipsel -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu -relocation-model=pic -mips-tail-calls=1\
-; RUN: | FileCheck %s -check-prefix=CHECK-NACL
; RUN: llc < %s -mtriple=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic -mips-tail-calls=1| FileCheck %s -check-prefix=NOODDSPREG
; RUN: llc < %s -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic -mips-tail-calls=1 | FileCheck %s -check-prefix=FP64-NOODDSPREG
@@ -103,11 +101,6 @@ entry:
; CHECK: lw $5
; CHECK: lw $4
-; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
-; CHECK-NACL-NOT: lw $14
-; CHECK-NACL-NOT: lw $15
-; CHECK-NACL-NOT: lw $24
-
%0 = load i32, ptr @gi0, align 4
%1 = load i32, ptr @gi1, align 4
%2 = load i32, ptr @gi2, align 4
@@ -146,11 +139,6 @@ entry:
; CHECK-DAG: sw $24
; CHECK-DAG: sw $3
-; t6, t7 and t8 are reserved in NaCl and cannot be used for fastcc.
-; CHECK-NACL-NOT: sw $14
-; CHECK-NACL-NOT: sw $15
-; CHECK-NACL-NOT: sw $24
-
store i32 %a0, ptr @g0, align 4
store i32 %a1, ptr @g1, align 4
store i32 %a2, ptr @g2, align 4
diff --git a/llvm/test/CodeGen/Mips/fp-indexed-ls.ll b/llvm/test/CodeGen/Mips/fp-indexed-ls.ll
index 8e20c8229847c..d1ec8fcbf3720 100644
--- a/llvm/test/CodeGen/Mips/fp-indexed-ls.ll
+++ b/llvm/test/CodeGen/Mips/fp-indexed-ls.ll
@@ -6,9 +6,6 @@
; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4
; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6
-; Check that [ls][dwu]xc1 are not emitted for nacl.
-; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
-
%struct.S = type <{ [4 x float] }>
%struct.S2 = type <{ [4 x double] }>
%struct.S3 = type <{ i8, float }>
@@ -43,8 +40,6 @@ entry:
; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS64R6: lwc1 $f0, 0($[[T3]])
-; CHECK-NACL-NOT: lwxc1
-
%arrayidx = getelementptr inbounds float, ptr %b, i32 %o
%0 = load float, ptr %arrayidx, align 4
ret float %0
@@ -74,8 +69,6 @@ entry:
; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS64R6: ldc1 $f0, 0($[[T3]])
-; CHECK-NACL-NOT: ldxc1
-
%arrayidx = getelementptr inbounds double, ptr %b, i32 %o
%0 = load double, ptr %arrayidx, align 8
ret double %0
@@ -127,8 +120,6 @@ entry:
; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
-; CHECK-NACL-NOT: swxc1
-
%0 = load float, ptr @gf, align 4
%arrayidx = getelementptr inbounds float, ptr %b, i32 %o
store float %0, ptr %arrayidx, align 4
@@ -157,8 +148,6 @@ entry:
; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS64R6-DAG: sdc1 $[[T0]], 0($[[T1]])
-; CHECK-NACL-NOT: sdxc1
-
%0 = load double, ptr @gd, align 8
%arrayidx = getelementptr inbounds double, ptr %b, i32 %o
store double %0, ptr %arrayidx, align 8
diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll
index e8771feefad33..c8270ed215484 100644
--- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll
+++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; Except for the NACL version which isn't parsed by update_llc_test_checks.py
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 \
; RUN: -mcpu=mips32r2 -mattr=+use-indirect-jump-hazard -relocation-model=pic \
diff --git a/llvm/test/CodeGen/Mips/longbranch.ll b/llvm/test/CodeGen/Mips/longbranch.ll
index d348f03295811..9eeff3152da35 100644
--- a/llvm/test/CodeGen/Mips/longbranch.ll
+++ b/llvm/test/CodeGen/Mips/longbranch.ll
@@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; Except for the NACL version which isn't parsed by update_llc_test_checks.py
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -O3 -relocation-model=pic < %s \
; RUN: | FileCheck %s -check-prefix=NOLONGBRANCH
@@ -27,11 +26,6 @@
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPSR6PIC
-
-; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \
-; RUN: | FileCheck %s -check-prefix=NACL
-
-
@x = external global i32
define void @test1(i32 signext %s) {
@@ -276,38 +270,6 @@ define void @test1(i32 signext %s) {
; MICROMIPSR6PIC-NEXT: $BB0_4: # %end
; MICROMIPSR6PIC-NEXT: jrc $ra
-; NACL-LABEL: test1:
-; NACL: # %bb.0:
-; NACL-NEXT: lui $2, %hi(_gp_disp)
-; NACL-NEXT: addiu $2, $2, %lo(_gp_disp)
-; NACL-NEXT: bnez $4, $BB0_3
-; NACL-NEXT: addu $2, $2, $25
-; NACL-NEXT: # %bb.1:
-; NACL-NEXT: addiu $sp, $sp, -8
-; NACL-NEXT: sw $ra, 0($sp)
-; NACL-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
-; NACL-NEXT: bal $BB0_2
-; NACL-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
-; NACL-NEXT: $BB0_2:
-; NACL-NEXT: addu $1, $ra, $1
-; NACL-NEXT: lw $ra, 0($sp)
-; NACL-NEXT: addiu $sp, $sp, 8
-; NACL-NEXT: jr $1
-; NACL-NEXT: nop
-; NACL-NEXT: $BB0_3:
-; NACL-NEXT: lw $1, %got(x)($2)
-; NACL-NEXT: addiu $2, $zero, 1
-; NACL-NEXT: sw $2, 0($1)
-; NACL-NEXT: .p2align 4
-; NACL-NEXT: $BB0_4:
-; NACL-NEXT: jr $ra
-; NACL-NEXT: nop
-
-
-; Check the NaCl version. Check that sp change is not in the branch delay slot
-; of "jr $1" instruction. Check that target of indirect branch "jr $1" is
-; bundle aligned.
-
entry:
%cmp = icmp eq i32 %s, 0
br i1 %cmp, label %end, label %then
diff --git a/llvm/test/CodeGen/Mips/nacl-align.ll b/llvm/test/CodeGen/Mips/nacl-align.ll
deleted file mode 100644
index 668b7a21e218a..0000000000000
--- a/llvm/test/CodeGen/Mips/nacl-align.ll
+++ /dev/null
@@ -1,99 +0,0 @@
-; RUN: llc -filetype=asm -mtriple=mipsel-none-nacl -relocation-model=static \
-; RUN: -O3 < %s | FileCheck %s
-
-
-; This test tests that NaCl functions are bundle-aligned.
-
-define void @test0() {
- ret void
-
-; CHECK: .p2align 4
-; CHECK-NOT: .p2align
-; CHECK-LABEL: test0:
-
-}
-
-
-; This test tests that blocks that are jumped to through jump table are
-; bundle-aligned.
-
-define i32 @test1(i32 %i) {
-entry:
- switch i32 %i, label %default [
- i32 0, label %bb1
- i32 1, label %bb2
- i32 2, label %bb3
- i32 3, label %bb4
- ]
-
-bb1:
- ret i32 111
-bb2:
- ret i32 222
-bb3:
- ret i32 333
-bb4:
- ret i32 444
-default:
- ret i32 555
-
-
-; CHECK-LABEL: test1:
-
-; CHECK: .p2align 4
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 111
-; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 333
-; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 444
-; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 222
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 555
-
-}
-
-
-; This test tests that a block whose address is taken is bundle-aligned in NaCl.
-
- at bb_array = constant [2 x ptr] [ptr blockaddress(@test2, %bb1),
- ptr blockaddress(@test2, %bb2)], align 4
-
-define i32 @test2(i32 %i) {
-entry:
- %elementptr = getelementptr inbounds [2 x ptr], ptr @bb_array, i32 0, i32 %i
- %0 = load ptr, ptr %elementptr, align 4
- indirectbr ptr %0, [label %bb1, label %bb2]
-
-bb1:
- ret i32 111
-bb2:
- ret i32 222
-
-
-; CHECK-LABEL: test2:
-
-; Note that there are two consecutive labels - one temporary and one for
-; basic block.
-
-; CHECK: .p2align 4
-; CHECK-NEXT: ${{[a-zA-Z0-9]+}}:
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 111
-; CHECK-NEXT: .p2align 4
-; CHECK-NEXT: ${{[a-zA-Z0-9]+}}:
-; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}:
-; CHECK-NEXT: jr $ra
-; CHECK-NEXT: addiu $2, $zero, 222
-
-}
diff --git a/llvm/test/CodeGen/Mips/nacl-branch-delay.ll b/llvm/test/CodeGen/Mips/nacl-branch-delay.ll
deleted file mode 100644
index 38348d8d49ec4..0000000000000
--- a/llvm/test/CodeGen/Mips/nacl-branch-delay.ll
+++ /dev/null
@@ -1,71 +0,0 @@
-; RUN: llc -filetype=asm -mtriple=mipsel-none-linux -relocation-model=static \
-; RUN: -O3 < %s | FileCheck %s
-
-; RUN: llc -filetype=asm -mtriple=mipsel-none-nacl -relocation-model=static \
-; RUN: -O3 < %s | FileCheck %s -check-prefix=CHECK-NACL
-
- at x = global i32 0, align 4
-declare void @f1(i32)
-declare void @f2()
-
-
-define void @test1() {
- %1 = load i32, ptr @x, align 4
- call void @f1(i32 %1)
- ret void
-
-
-; CHECK-LABEL: test1
-
-; We first make sure that for non-NaCl targets branch-delay slot contains
-; dangerous instructions.
-
-; Check that branch-delay slot is used to load argument from x before function
-; call.
-
-; CHECK: jal
-; CHECK-NEXT: lw $4, %lo(x)(${{[0-9]+}})
-
-; Check that branch-delay slot is used for adjusting sp before return.
-
-; CHECK: jr $ra
-; CHECK-NEXT: addiu $sp, $sp, {{[0-9]+}}
-
-
-; For NaCl, check that branch-delay slot doesn't contain dangerous instructions.
-
-; CHECK-NACL: jal
-; CHECK-NACL-NEXT: nop
-
-; CHECK-NACL: jr $ra
-; CHECK-NACL-NEXT: nop
-}
-
-
-define void @test2() {
- store i32 1, ptr @x, align 4
- call void @f2()
- ret void
-
-
-; CHECK-LABEL: test2
-
-; Check that branch-delay slot is used for storing to x before function call.
-
-; CHECK: jal
-; CHECK-NEXT: sw ${{[0-9]+}}, %lo(x)(${{[0-9]+}})
-
-; Check that branch-delay slot is used for adjusting sp before return.
-
-; CHECK: jr $ra
-; CHECK-NEXT: addiu $sp, $sp, {{[0-9]+}}
-
-
-; For NaCl, check that branch-delay slot doesn't contain dangerous instructions.
-
-; CHECK-NACL: jal
-; CHECK-NACL-NEXT: nop
-
-; CHECK-NACL: jr $ra
-; CHECK-NACL-NEXT: nop
-}
diff --git a/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll b/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
deleted file mode 100644
index b03418dff6ccc..0000000000000
--- a/llvm/test/CodeGen/Mips/nacl-reserved-regs.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; RUN: llc -mtriple=mipsel -O3 < %s | FileCheck %s
-; RUN: llc -mtriple=mipsel-none-nacl-gnu -O3 < %s \
-; RUN: | FileCheck %s -check-prefix=CHECK-NACL
-
- at var = external global i32
-
-define void @f() {
- %val1 = load volatile i32, ptr @var
- %val2 = load volatile i32, ptr @var
- %val3 = load volatile i32, ptr @var
- %val4 = load volatile i32, ptr @var
- %val5 = load volatile i32, ptr @var
- %val6 = load volatile i32, ptr @var
- %val7 = load volatile i32, ptr @var
- %val8 = load volatile i32, ptr @var
- %val9 = load volatile i32, ptr @var
- %val10 = load volatile i32, ptr @var
- %val11 = load volatile i32, ptr @var
- %val12 = load volatile i32, ptr @var
- %val13 = load volatile i32, ptr @var
- %val14 = load volatile i32, ptr @var
- %val15 = load volatile i32, ptr @var
- %val16 = load volatile i32, ptr @var
- store volatile i32 %val1, ptr @var
- store volatile i32 %val2, ptr @var
- store volatile i32 %val3, ptr @var
- store volatile i32 %val4, ptr @var
- store volatile i32 %val5, ptr @var
- store volatile i32 %val6, ptr @var
- store volatile i32 %val7, ptr @var
- store volatile i32 %val8, ptr @var
- store volatile i32 %val9, ptr @var
- store volatile i32 %val10, ptr @var
- store volatile i32 %val11, ptr @var
- store volatile i32 %val12, ptr @var
- store volatile i32 %val13, ptr @var
- store volatile i32 %val14, ptr @var
- store volatile i32 %val15, ptr @var
- store volatile i32 %val16, ptr @var
- ret void
-
-; Check that t6, t7 and t8 are used in non-NaCl code.
-; CHECK: lw $14
-; CHECK: lw $15
-; CHECK: lw $24
-
-; t6, t7 and t8 are reserved in NaCl.
-; CHECK-NACL-NOT: lw $14
-; CHECK-NACL-NOT: lw $15
-; CHECK-NACL-NOT: lw $24
-}
diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
index 23924b2fb2f8c..1924d678bf9fd 100644
--- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
+++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-1.ll
@@ -3,7 +3,7 @@
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
; Triple tweaked so we get 16-byte stack alignment and better test coverage.
-target triple = "armv7m-none-nacl-android"
+target triple = "armv7m-linux-android"
; -Oz
; volatile int a, b, c, d, e, f, g, h, i;
diff --git a/llvm/test/CodeGen/X86/constructor.ll b/llvm/test/CodeGen/X86/constructor.ll
index 3133979b32f83..2efb5fbd12a67 100644
--- a/llvm/test/CodeGen/X86/constructor.ll
+++ b/llvm/test/CodeGen/X86/constructor.ll
@@ -5,7 +5,6 @@
; RUN: llc -mtriple x86_64-pc-linux < %s | FileCheck --check-prefix=INIT-ARRAY %s
; RUN: llc -mtriple x86_64-unknown-freebsd < %s | FileCheck --check-prefix=INIT-ARRAY %s
; RUN: llc -mtriple x86_64-pc-solaris2.11 < %s | FileCheck --check-prefix=INIT-ARRAY %s
-; RUN: llc -mtriple x86_64-unknown-nacl < %s | FileCheck --check-prefix=NACL %s
; RUN: llc -mtriple i586-intel-elfiamcu -use-ctors < %s | FileCheck %s --check-prefix=MCU-CTORS
; RUN: llc -mtriple i586-intel-elfiamcu < %s | FileCheck %s --check-prefix=MCU-INIT-ARRAY
; RUN: llc -mtriple x86_64-win32-gnu < %s | FileCheck --check-prefix=COFF-CTOR %s
@@ -62,18 +61,6 @@ entry:
; INIT-ARRAY-NEXT: .quad i
; INIT-ARRAY-NEXT: .quad j
-; NACL: .section .init_array.15,"awG", at init_array,v,comdat
-; NACL-NEXT: .p2align 2
-; NACL-NEXT: .long g
-; NACL-NEXT: .section .init_array.55555,"awG", at init_array,v,comdat
-; NACL-NEXT: .p2align 2
-; NACL-NEXT: .long h
-; NACL-NEXT: .section .init_array,"aw", at init_array
-; NACL-NEXT: .p2align 2
-; NACL-NEXT: .long f
-; NACL-NEXT: .long i
-; NACL-NEXT: .long j
-
; MCU-CTORS: .section .ctors,"aw", at progbits
; MCU-INIT-ARRAY: .section .init_array,"aw", at init_array
diff --git a/llvm/test/CodeGen/X86/fast-isel-x32.ll b/llvm/test/CodeGen/X86/fast-isel-x32.ll
index 23f6304c88d28..e01cebecdbb0a 100644
--- a/llvm/test/CodeGen/X86/fast-isel-x32.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-x32.ll
@@ -1,5 +1,4 @@
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s
; Test that alloca addresses are materialized with the right size instruction.
diff --git a/llvm/test/CodeGen/X86/frameaddr.ll b/llvm/test/CodeGen/X86/frameaddr.ll
index 7f2f9b8bd6fd0..33c9e3855c108 100644
--- a/llvm/test/CodeGen/X86/frameaddr.ll
+++ b/llvm/test/CodeGen/X86/frameaddr.ll
@@ -5,8 +5,6 @@
; RUN: llc < %s -mtriple=x86_64-unknown -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-X32ABI
-; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64
-; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=CHECK-NACL64
define ptr @test1() nounwind {
entry:
@@ -34,10 +32,6 @@ entry:
; CHECK-X32ABI-NEXT: movl %ebp, %eax
; CHECK-X32ABI-NEXT: popq %rbp
; CHECK-X32ABI-NEXT: ret
-; CHECK-NACL64-LABEL: test1
-; CHECK-NACL64: pushq %rbp
-; CHECK-NACL64-NEXT: movq %rsp, %rbp
-; CHECK-NACL64-NEXT: movl %ebp, %eax
%0 = tail call ptr @llvm.frameaddress(i32 0)
ret ptr %0
}
@@ -71,11 +65,6 @@ entry:
; CHECK-X32ABI-NEXT: movl (%eax), %eax
; CHECK-X32ABI-NEXT: popq %rbp
; CHECK-X32ABI-NEXT: ret
-; CHECK-NACL64-LABEL: test2
-; CHECK-NACL64: pushq %rbp
-; CHECK-NACL64-NEXT: movq %rsp, %rbp
-; CHECK-NACL64-NEXT: movl (%ebp), %eax
-; CHECK-NACL64-NEXT: movl (%eax), %eax
%0 = tail call ptr @llvm.frameaddress(i32 2)
ret ptr %0
}
diff --git a/llvm/test/CodeGen/X86/lea-2.ll b/llvm/test/CodeGen/X86/lea-2.ll
index a48c02ff3e0b7..0883a8e726e25 100644
--- a/llvm/test/CodeGen/X86/lea-2.ll
+++ b/llvm/test/CodeGen/X86/lea-2.ll
@@ -2,7 +2,6 @@
; RUN: llc < %s -mtriple=i686-linux | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=X64
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefix=X64
-; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=X64
; The computation of %t4 should match a single lea, without using actual add instructions.
diff --git a/llvm/test/CodeGen/X86/lea-3.ll b/llvm/test/CodeGen/X86/lea-3.ll
index b7f1c4ae11549..2cbefc0689c11 100644
--- a/llvm/test/CodeGen/X86/lea-3.ll
+++ b/llvm/test/CodeGen/X86/lea-3.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=WIN32
define i64 @test2(i64 %a) {
diff --git a/llvm/test/CodeGen/X86/lea-4.ll b/llvm/test/CodeGen/X86/lea-4.ll
index e1f0b73c33ffb..c33697e0abf3d 100644
--- a/llvm/test/CodeGen/X86/lea-4.ll
+++ b/llvm/test/CodeGen/X86/lea-4.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s
define zeroext i16 @t1(i32 %on_off) nounwind {
; CHECK-LABEL: t1:
diff --git a/llvm/test/CodeGen/X86/lea-5.ll b/llvm/test/CodeGen/X86/lea-5.ll
index 908ec3eae7f65..39051eac45d7d 100644
--- a/llvm/test/CodeGen/X86/lea-5.ll
+++ b/llvm/test/CodeGen/X86/lea-5.ll
@@ -4,7 +4,6 @@
; RUN: llc < %s -mtriple=x86_64-linux -O2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -O2 | FileCheck %s -check-prefix=X32
-; RUN: llc < %s -mtriple=x86_64-nacl -O2 | FileCheck %s -check-prefix=X32
; Function Attrs: nounwind readnone uwtable
define void @foo(i32 %x, i32 %d) #0 {
diff --git a/llvm/test/CodeGen/X86/lea.ll b/llvm/test/CodeGen/X86/lea.ll
index 33d121f6849ba..28c66b94a69eb 100644
--- a/llvm/test/CodeGen/X86/lea.ll
+++ b/llvm/test/CodeGen/X86/lea.ll
@@ -2,7 +2,6 @@
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=LINUX
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefixes=WIN
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefixes=LINUX
-; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefixes=LINUX
define i32 @test1(i32 %x) nounwind {
; LINUX-LABEL: test1:
diff --git a/llvm/test/CodeGen/X86/stack-align2.ll b/llvm/test/CodeGen/X86/stack-align2.ll
index 99f36d2ca8b7a..095a9090ed08f 100644
--- a/llvm/test/CodeGen/X86/stack-align2.ll
+++ b/llvm/test/CodeGen/X86/stack-align2.ll
@@ -3,13 +3,11 @@
; RUN: llc < %s -mcpu=generic -mtriple=i386-netbsd | FileCheck %s -check-prefix=NETBSD-I386
; RUN: llc < %s -mcpu=generic -mtriple=i686-apple-darwin8 | FileCheck %s -check-prefix=DARWIN-I386
; RUN: llc < %s -mcpu=generic -mtriple=i386-pc-solaris2.11 | FileCheck %s -check-prefix=SOLARIS-I386
-; RUN: llc < %s -mcpu=generic -mtriple=i386-nacl | FileCheck %s -check-prefix=NACL-I386
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s -check-prefix=LINUX-X86_64
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-kfreebsd | FileCheck %s -check-prefix=KFREEBSD-X86_64
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-netbsd | FileCheck %s -check-prefix=NETBSD-X86_64
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin8 | FileCheck %s -check-prefix=DARWIN-X86_64
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-solaris2.11 | FileCheck %s -check-prefix=SOLARIS-X86_64
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-nacl | FileCheck %s -check-prefix=NACL-X86_64
define i32 @test() nounwind {
entry:
@@ -19,7 +17,6 @@ entry:
; LINUX-I386: subl $12, %esp
; KFREEBSD-I386: subl $12, %esp
; DARWIN-I386: subl $12, %esp
-; NACL-I386: subl $12, %esp
; NETBSD-I386-NOT: subl {{.*}}, %esp
; SOLARIS-I386-NOT: subl {{.*}}, %esp
@@ -27,8 +24,6 @@ entry:
; LINUX-X86_64-NOT: subq {{.*}}, %rsp
; DARWIN-X86_64: pushq %{{.*}}
; DARWIN-X86_64-NOT: subq {{.*}}, %rsp
-; NACL-X86_64: pushq %{{.*}}
-; NACL-X86_64-NOT: subq {{.*}}, %rsp
; NETBSD-X86_64: pushq %{{.*}}
; NETBSD-X86_64-NOT: subq {{.*}}, %rsp
; SOLARIS-X86_64: pushq %{{.*}}
diff --git a/llvm/test/CodeGen/X86/x86-64-baseptr.ll b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
index 020004def6e7a..62c63d5defe60 100644
--- a/llvm/test/CodeGen/X86/x86-64-baseptr.ll
+++ b/llvm/test/CodeGen/X86/x86-64-baseptr.ll
@@ -2,14 +2,6 @@
; RUN: llc -mtriple=x86_64-pc-linux -stackrealign -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -stackrealign -verify-machineinstrs < %s | FileCheck -check-prefix=X32ABI %s
-; This should run with NaCl as well ( -mtriple=x86_64-pc-nacl ) but currently doesn't due to PR22655
-
-; Make sure the correct register gets set up as the base pointer
-; This should be rbx for x64 and 64-bit NaCl and ebx for x32
-; NACL-LABEL: base
-; NACL: subq $32, %rsp
-; NACL: movq %rsp, %rbx
-
declare i32 @helper() nounwind
define void @base() #0 {
; CHECK-LABEL: base:
diff --git a/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll b/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
index bceebdc9ad7d2..26be80ea58949 100644
--- a/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
+++ b/llvm/test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll
@@ -1,6 +1,5 @@
; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-linux-gnux32 < %s | FileCheck -check-prefix=X32ABI %s
-; RUN: llc -verify-machineinstrs -mtriple=x86_64-pc-nacl < %s | FileCheck -check-prefix=NACL %s
; x32 uses %esp, %ebp as stack and frame pointers
@@ -14,12 +13,6 @@
; X32ABI: movl %esp, %ebp
; X32ABI: movl %edi, -4(%ebp)
; X32ABI: popq %rbp
-; NACL-LABEL: foo
-; NACL: pushq %rbp
-; NACL: movq %rsp, %rbp
-; NACL: movl %edi, -4(%rbp)
-; NACL: popq %rbp
-
define void @foo(ptr %a) #0 {
entry:
@@ -30,5 +23,3 @@ entry:
}
attributes #0 = { nounwind uwtable "frame-pointer"="all"}
-
-
diff --git a/llvm/test/MC/ARM/arm_instructions.s b/llvm/test/MC/ARM/arm_instructions.s
index a4c100ee68f90..ab532ec321078 100644
--- a/llvm/test/MC/ARM/arm_instructions.s
+++ b/llvm/test/MC/ARM/arm_instructions.s
@@ -1,14 +1,8 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s \
@ RUN: | FileCheck %s -check-prefix=ALL
-@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7-unknown-nacl -show-encoding %s \
-@ RUN: | FileCheck %s -check-prefix=NACL
-@ RUN: llvm-mc -mcpu=cortex-a8 -mattr=+nacl-trap -triple armv7 -show-encoding %s \
-@ RUN: | FileCheck %s -check-prefix=NACL
@ ALL: trap
@ ALL: encoding: [0xfe,0xde,0xff,0xe7]
-@ NACL: trap
-@ NACL: encoding: [0xf0,0xde,0xfe,0xe7]
trap
@ CHECK: bx lr
diff --git a/llvm/test/MC/Mips/nacl-mask.s b/llvm/test/MC/Mips/nacl-mask.s
deleted file mode 100644
index 17226475c2135..0000000000000
--- a/llvm/test/MC/Mips/nacl-mask.s
+++ /dev/null
@@ -1,319 +0,0 @@
-# RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
-# RUN: | llvm-objdump --no-print-imm-hex -d -z --no-show-raw-insn - | FileCheck %s
-
-# This test tests that address-masking sandboxing is added when given assembly
-# input.
-
-
-# Test that address-masking sandboxing is added before indirect branches and
-# returns.
-
- .align 4
-test1:
- .set noreorder
-
- jr $a0
- nop
- jr $ra
- nop
-
-# CHECK-LABEL: <test1>:
-
-# CHECK: and $4, $4, $14
-# CHECK-NEXT: jr $4
-
-# Check that additional nop is inserted, to align mask and jr to the next
-# bundle.
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-
-# CHECK: and $ra, $ra, $14
-# CHECK-NEXT: jr $ra
-
-
-
-# Test that address-masking sandboxing is added before load instructions.
-
- .align 4
-test2:
- .set noreorder
-
- lb $4, 0($1)
- nop
- lbu $4, 0($2)
- lh $4, 0($3)
- lhu $1, 0($4)
- lw $4, 0($5)
- lwc1 $f0, 0($6)
- ldc1 $f2, 0($7)
- ll $4, 0($8)
- lwl $4, 0($9)
- lwr $4, 0($10)
-
- lw $4, 0($sp)
- lw $4, 0($t8)
-
-# CHECK-LABEL: <test2>:
-
-# CHECK: and $1, $1, $15
-# CHECK-NEXT: lb $4, 0($1)
-
-# Check that additional nop is inserted, to align mask and load to the next
-# bundle.
-
-# CHECK: nop
-# CHECK: nop
-
-# CHECK: and $2, $2, $15
-# CHECK-NEXT: lbu $4, 0($2)
-
-# CHECK: and $3, $3, $15
-# CHECK-NEXT: lh $4, 0($3)
-
-# CHECK: and $4, $4, $15
-# CHECK-NEXT: lhu $1, 0($4)
-
-# CHECK: and $5, $5, $15
-# CHECK-NEXT: lw $4, 0($5)
-
-# CHECK: and $6, $6, $15
-# CHECK-NEXT: lwc1 $f0, 0($6)
-
-# CHECK: and $7, $7, $15
-# CHECK-NEXT: ldc1 $f2, 0($7)
-
-# CHECK: and $8, $8, $15
-# CHECK-NEXT: ll $4, 0($8)
-
-# CHECK: and $9, $9, $15
-# CHECK-NEXT: lwl $4, 0($9)
-
-# CHECK: and $10, $10, $15
-# CHECK-NEXT: lwr $4, 0($10)
-
-
-# Check that loads where base register is $sp or $t8 (thread pointer register)
-# are not masked.
-
-# CHECK-NOT: and
-# CHECK: lw $4, 0($sp)
-# CHECK-NOT: and
-# CHECK: lw $4, 0($24)
-
-
-
-# Test that address-masking sandboxing is added before store instructions.
-
- .align 4
-test3:
- .set noreorder
-
- sb $4, 0($1)
- nop
- sh $4, 0($2)
- sw $4, 0($3)
- swc1 $f0, 0($4)
- sdc1 $f2, 0($5)
- swl $4, 0($6)
- swr $4, 0($7)
- sc $4, 0($8)
-
- sw $4, 0($sp)
- sw $4, 0($t8)
-
-# CHECK-LABEL: <test3>:
-
-# CHECK: and $1, $1, $15
-# CHECK-NEXT: sb $4, 0($1)
-
-# Check that additional nop is inserted, to align mask and store to the next
-# bundle.
-
-# CHECK: nop
-# CHECK: nop
-
-# CHECK: and $2, $2, $15
-# CHECK-NEXT: sh $4, 0($2)
-
-# CHECK: and $3, $3, $15
-# CHECK-NEXT: sw $4, 0($3)
-
-# CHECK: and $4, $4, $15
-# CHECK-NEXT: swc1 $f0, 0($4)
-
-# CHECK: and $5, $5, $15
-# CHECK-NEXT: sdc1 $f2, 0($5)
-
-# CHECK: and $6, $6, $15
-# CHECK-NEXT: swl $4, 0($6)
-
-# CHECK: and $7, $7, $15
-# CHECK-NEXT: swr $4, 0($7)
-
-# CHECK: and $8, $8, $15
-# CHECK-NEXT: sc $4, 0($8)
-
-
-# Check that stores where base register is $sp or $t8 (thread pointer register)
-# are not masked.
-
-# CHECK-NOT: and
-# CHECK: sw $4, 0($sp)
-# CHECK-NOT: and
-# CHECK: sw $4, 0($24)
-
-
-
-# Test that address-masking sandboxing is added after instructions that change
-# stack pointer.
-
- .align 4
-test4:
- .set noreorder
-
- addiu $sp, $sp, 24
- nop
- addu $sp, $sp, $1
- lw $sp, 0($2)
- lw $sp, 123($sp)
- sw $sp, 123($sp)
-
-# CHECK-LABEL: <test4>:
-
-# CHECK: addiu $sp, $sp, 24
-# CHECK-NEXT: and $sp, $sp, $15
-
-# Check that additional nop is inserted, to align instruction and mask to the
-# next bundle.
-
-# CHECK: nop
-# CHECK: nop
-
-# CHECK: addu $sp, $sp, $1
-# CHECK-NEXT: and $sp, $sp, $15
-
-# Since we next check sandboxing sequence which consists of 3 instructions,
-# check that 2 additional nops are inserted, to align it to the next bundle.
-
-# CHECK: nop
-# CHECK: nop
-
-
-# Check that for instructions that change stack-pointer and load from memory
-# masks are added before and after the instruction.
-
-# CHECK: and $2, $2, $15
-# CHECK-NEXT: lw $sp, 0($2)
-# CHECK-NEXT: and $sp, $sp, $15
-
-# For loads where $sp is destination and base, check that mask is added after
-# but not before.
-
-# CHECK-NOT: and
-# CHECK: lw $sp, 123($sp)
-# CHECK-NEXT: and $sp, $sp, $15
-
-# For stores where $sp is destination and base, check that mask is added neither
-# before nor after.
-
-# CHECK-NOT: and
-# CHECK: sw $sp, 123($sp)
-# CHECK-NOT: and
-
-
-
-# Test that call + branch delay is aligned at bundle end. Test that mask is
-# added before indirect calls.
-
- .align 4
-test5:
- .set noreorder
-
- jal func1
- addiu $4, $zero, 1
-
- nop
- bal func2
- addiu $4, $zero, 2
-
- nop
- nop
- bltzal $t1, func3
- addiu $4, $zero, 3
-
- nop
- nop
- nop
- bgezal $t2, func4
- addiu $4, $zero, 4
-
- jalr $t9
- addiu $4, $zero, 5
-
-
-# CHECK: nop
-# CHECK-NEXT: nop
-# CHECK-LABEL: <test5>:
-# CHECK-NEXT: jal
-# CHECK-NEXT: addiu $4, $zero, 1
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-# CHECK-NEXT: bal
-# CHECK-NEXT: addiu $4, $zero, 2
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-# CHECK-NEXT: bltzal
-# CHECK-NEXT: addiu $4, $zero, 3
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-# CHECK-NEXT: bgezal
-# CHECK-NEXT: addiu $4, $zero, 4
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: and $25, $25, $14
-# CHECK-NEXT: jalr $25
-# CHECK-NEXT: addiu $4, $zero, 5
-
-
-
-# Test that we can put non-dangerous loads and stores in branch delay slot.
-
- .align 4
-test6:
- .set noreorder
-
- jal func1
- sw $4, 0($sp)
-
- bal func2
- lw $5, 0($t8)
-
- jalr $t9
- sw $sp, 0($sp)
-
-
-
-# CHECK: nop
-# CHECK-NEXT: nop
-# CHECK-LABEL: <test6>:
-# CHECK-NEXT: jal
-# CHECK-NEXT: sw $4, 0($sp)
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: nop
-# CHECK-NEXT: bal
-# CHECK-NEXT: lw $5, 0($24)
-
-# CHECK-NEXT: nop
-# CHECK-NEXT: and $25, $25, $14
-# CHECK-NEXT: jalr
-# CHECK-NEXT: sw $sp, 0($sp)
diff --git a/llvm/test/MC/X86/AlignedBundling/labeloffset.s b/llvm/test/MC/X86/AlignedBundling/labeloffset.s
index 2850aba718430..7f6150a8aa17c 100644
--- a/llvm/test/MC/X86/AlignedBundling/labeloffset.s
+++ b/llvm/test/MC/X86/AlignedBundling/labeloffset.s
@@ -1,8 +1,4 @@
# RUN: llvm-mc -triple=i686-linux -filetype=obj %s -o - | \
-# RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn -r - | FileCheck %s
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - | \
-# RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn -r - | FileCheck %s
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - | \
# RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn -r - | FileCheck %s
.bundle_align_mode 5
diff --git a/llvm/test/MC/X86/AlignedBundling/rodata-section.s b/llvm/test/MC/X86/AlignedBundling/rodata-section.s
deleted file mode 100644
index 6c2b41a6f8034..0000000000000
--- a/llvm/test/MC/X86/AlignedBundling/rodata-section.s
+++ /dev/null
@@ -1,30 +0,0 @@
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj %s -o - \
-# RUN: | llvm-objdump --no-print-imm-hex -d --no-show-raw-insn - | FileCheck %s
-# RUN: llvm-mc -triple=i686-nacl -filetype=obj -mc-relax-all %s -o - \
-# RUN: | llvm-objdump --no-print-imm-hex -d --no-show-raw-insn - | FileCheck %s
-
- .bundle_align_mode 5
- .text
- .align 32, 0x90
-# CHECK: 0: movl $14, 8(%esp)
- movl $.str2, 8(%esp)
-# CHECK: 8: movl $7, 4(%esp)
- movl $.str1, 4(%esp)
-# CHECK: 10: movl $0, (%esp)
- movl $.str, (%esp)
-
- .type .str, at object
- .section .rodata,"a", at progbits
-.str:
- .asciz "hello1"
- .size .str, 7
-
- .type .str1, at object
-.str1:
- .asciz "hello2"
- .size .str1, 7
-
- .type .str2, at object
-.str2:
- .asciz "hello3"
- .size .str2, 7
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index dcffc9471705f..4d1cb2629f6eb 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -959,10 +959,6 @@ TEST(TargetParserTest, ARMparseArchVersion) {
TEST(TargetParserTest, getARMCPUForArch) {
// Platform specific defaults.
- {
- llvm::Triple Triple("arm--nacl");
- EXPECT_EQ("cortex-a8", ARM::getARMCPUForArch(Triple));
- }
{
llvm::Triple Triple("arm--openbsd");
EXPECT_EQ("cortex-a8", ARM::getARMCPUForArch(Triple));
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