[llvm] Remove iOS 5 check for tailcalls on ARM (PR #133354)

[via llvm-commits]

https://github.com/Un1q32 updated https://github.com/llvm/llvm-project/pull/133354

>From a5c18987dc78a40ae5041a6f8c0161e6aa097fcb Mon Sep 17 00:00:00 2001
From: Un1q32 <joey.t.reinhart at gmail.com>
Date: Fri, 28 Mar 2025 21:13:49 +0000
Subject: [PATCH 1/2] Remove iOS 5 check for tailcalls on ARM

---
 llvm/lib/Target/ARM/ARMSubtarget.cpp | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 893084785e6f0..759070c6f08da 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -226,9 +226,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
 
   SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps();
 
-  if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
-    SupportsTailCall = false;
-
   switch (IT) {
   case DefaultIT:
     RestrictIT = false;

>From 8431e8629f4127ab39217906ad66715694eac228 Mon Sep 17 00:00:00 2001
From: Un1q32 <joey.t.reinhart at gmail.com>
Date: Sat, 29 Mar 2025 00:13:38 +0000
Subject: [PATCH 2/2] fix tests

---
 llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll | 4 ++--
 llvm/test/CodeGen/ARM/ldm.ll                    | 8 ++++----
 llvm/test/CodeGen/ARM/zextload_demandedbits.ll  | 5 ++---
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
index ff1e769600d38..b3b6c77f9bb8f 100644
--- a/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
+++ b/llvm/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
@@ -9,8 +9,8 @@ entry:
 ; CHECK: mov r7, sp
 ; CHECK: bl _foo
 ; CHECK: bl _foo
-; CHECK: bl _foo
-; CHECK: pop {r7, pc}
+; CHECK: pop
+; CHECK: b
 
   %0 = tail call ptr @foo(ptr %x) nounwind
   %1 = tail call ptr @foo(ptr %0) nounwind
diff --git a/llvm/test/CodeGen/ARM/ldm.ll b/llvm/test/CodeGen/ARM/ldm.ll
index 2f7486020890d..2d2fc578cf106 100644
--- a/llvm/test/CodeGen/ARM/ldm.ll
+++ b/llvm/test/CodeGen/ARM/ldm.ll
@@ -5,9 +5,9 @@
 
 define i32 @t1() {
 ; CHECK-LABEL: t1:
-; CHECK: pop
+; CHECK: ldrd
 ; V4T-LABEL: t1:
-; V4T: pop
+; V4T: ldm
         %tmp = load i32, ptr @X            ; <i32> [#uses=1]
         %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 1)           ; <i32> [#uses=1]
         %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 )                ; <i32> [#uses=1]
@@ -16,9 +16,9 @@ define i32 @t1() {
 
 define i32 @t2() {
 ; CHECK-LABEL: t2:
-; CHECK: pop
+; CHECK: ldm
 ; V4T-LABEL: t2:
-; V4T: pop
+; V4T: ldm
         %tmp = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 2)            ; <i32> [#uses=1]
         %tmp3 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 3)           ; <i32> [#uses=1]
         %tmp5 = load i32, ptr getelementptr ([0 x i32], ptr @X, i32 0, i32 4)           ; <i32> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/zextload_demandedbits.ll b/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
index 8519d30b7dabf..88136ae020400 100644
--- a/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
+++ b/llvm/test/CodeGen/ARM/zextload_demandedbits.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple="arm-apple-ios3.0.0" | FileCheck %s
+; RUN: llc < %s -mtriple="armv4t-apple-ios3.0.0" | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 
@@ -10,8 +10,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
 ; CHECK: quux
 ; CHECK: lsl
 ; CHECK: asr
-; CHECK: bl
-; CHECK: pop
+; CHECK: b
 define void @quux(ptr %arg) {
 bb:
   %tmp1 = getelementptr inbounds %struct.eggs, ptr %arg, i32 0, i32 1