[llvm] [WebAssembly] Add more lowerings for wide-arithmetic (PR #132430)

[Derek Schuff via llvm-commits]

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@@ -1794,10 +1809,33 @@ SDValue WebAssemblyTargetLowering::LowerMUL_LOHI(SDValue Op,
   }
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
-  SDValue Hi =
+  SDValue Lo =
       DAG.getNode(Opcode, DL, DAG.getVTList(MVT::i64, MVT::i64), LHS, RHS);
-  SDValue Lo(Hi.getNode(), 1);
-  SDValue Ops[] = {Hi, Lo};
+  SDValue Hi(Lo.getNode(), 1);
+  SDValue Ops[] = {Lo, Hi};
+  return DAG.getMergeValues(Ops, DL);
+}
+
+// Lowers `UADDO` intrinsics to an `i64.add128` instruction when it's enabled.
+//
+// This enables generating a single wasm instruction for this operation where
+// the upper bits of both operands are constant zeros. The upper bits of the
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dschuff wrote:

I think this comment might be clearer if you called it the "upper half" rather than "upper bits" since when I first read this I was thinking in terms of the most significant bits (and as then briefly confused since it's of course the least significant bit of the upper half that might be set). But maybe that's just me, feel free to leave it if you disagree.

https://github.com/llvm/llvm-project/pull/132430