[llvm] d6d559c - [RISCV] Add zvfhmin to zipeven/zipodd shuffle tests per review suggestion

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2025-03-28T11:08:14-07:00
New Revision: d6d559cc090b775649f1de6f6bfcc029184d4fb5

URL: https://github.com/llvm/llvm-project/commit/d6d559cc090b775649f1de6f6bfcc029184d4fb5
DIFF: https://github.com/llvm/llvm-project/commit/d6d559cc090b775649f1de6f6bfcc029184d4fb5.diff

LOG: [RISCV] Add zvfhmin to zipeven/zipodd shuffle tests per review suggestion

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
index 4dde731249bd6..c97f11301a05a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-zipeven-zipodd.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 define <4 x i32> @zipeven_v4i32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: zipeven_v4i32:
@@ -41,29 +41,12 @@ entry:
 }
 
 define <4 x half> @zipeven_v4f16(<4 x half> %a, <4 x half> %b) {
-; RV32-LABEL: zipeven_v4f16:
-; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    lh a3, 0(a1)
-; RV32-NEXT:    lh a4, 0(a2)
-; RV32-NEXT:    lh a1, 8(a1)
-; RV32-NEXT:    lh a2, 8(a2)
-; RV32-NEXT:    sh a3, 0(a0)
-; RV32-NEXT:    sh a4, 2(a0)
-; RV32-NEXT:    sh a1, 4(a0)
-; RV32-NEXT:    sh a2, 6(a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: zipeven_v4f16:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    lh a3, 0(a1)
-; RV64-NEXT:    lh a4, 0(a2)
-; RV64-NEXT:    lh a1, 16(a1)
-; RV64-NEXT:    lh a2, 16(a2)
-; RV64-NEXT:    sh a3, 0(a0)
-; RV64-NEXT:    sh a4, 2(a0)
-; RV64-NEXT:    sh a1, 4(a0)
-; RV64-NEXT:    sh a2, 6(a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: zipeven_v4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
+; CHECK-NEXT:    vmv.v.i v0, 10
+; CHECK-NEXT:    vslideup.vi v8, v9, 1, v0.t
+; CHECK-NEXT:    ret
 entry:
   %c = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
   ret <4 x half> %c
@@ -247,3 +230,6 @@ define <16 x i64> @zipodd_v16i64(<16 x i64> %v1, <16 x i64> %v2) {
   %out = shufflevector <16 x i64> %v1, <16 x i64> %v2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
   ret <16 x i64> %out
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32: {{.*}}
+; RV64: {{.*}}