[llvm] [RISCV] Rename operands used for branch and compressed jump targets. NFC (PR #133364)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 28 10:07:07 PDT 2025
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/133364
>From 769e1c59890623c9277322058b743573477498c0 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 27 Mar 2025 20:55:15 -0700
Subject: [PATCH] [RISCV] Rename operands used for branch and compressed jump
targets. NFC
The current names look just like predicates we use for regular
immediates, but branches and jumps also allow bare symbols.
While I was there I realized I could use PredicateMethod to have
the AsmMatcher directly call the template function we use in the
asm parser.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 16 ++----
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 43 +++++++++-------
llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 50 +++++++++----------
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 8 +--
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 5 +-
5 files changed, 60 insertions(+), 62 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 3c225fb38cb19..51938baab37f5 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -967,8 +967,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_None;
}
- bool isSImm9Lsb0() const { return isBareSimmNLsb0<9>(); }
-
bool isUImm9Lsb000() const {
if (!isImm())
return false;
@@ -1026,8 +1024,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_TLSDESC_ADD_LO);
}
- bool isSImm12Lsb0() const { return isBareSimmNLsb0<12>(); }
-
bool isSImm12Lsb00000() const {
if (!isImm())
return false;
@@ -1039,8 +1035,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_None;
}
- bool isSImm13Lsb0() const { return isBareSimmNLsb0<13>(); }
-
bool isSImm10Lsb0000NonZero() const {
if (!isImm())
return false;
@@ -1114,8 +1108,6 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_TLSDESC_HI);
}
- bool isSImm21Lsb0JAL() const { return isBareSimmNLsb0<21>(); }
-
bool isImmZero() const {
if (!isImm())
return false;
@@ -1728,7 +1720,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 8) - 8,
"immediate must be a multiple of 8 bytes in the range");
- case Match_InvalidSImm9Lsb0:
+ case Match_InvalidBareSImm9Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,
"immediate must be a multiple of 2 bytes in the range");
@@ -1758,7 +1750,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
"operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an "
"integer in the range");
- case Match_InvalidSImm12Lsb0:
+ case Match_InvalidBareSImm12Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 2,
"immediate must be a multiple of 2 bytes in the range");
@@ -1766,7 +1758,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 32,
"immediate must be a multiple of 32 bytes in the range");
- case Match_InvalidSImm13Lsb0:
+ case Match_InvalidBareSImm13Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2,
"immediate must be a multiple of 2 bytes in the range");
@@ -1789,7 +1781,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
"%pcrel_hi/%got_pcrel_hi/%tls_ie_pcrel_hi/%tls_gd_pcrel_hi specifier "
"or "
"an integer in the range");
- case Match_InvalidSImm21Lsb0JAL:
+ case Match_InvalidBareSImm21Lsb0:
return generateImmOutOfRangeError(
Operands, ErrorInfo, -(1 << 20), (1 << 20) - 2,
"immediate must be a multiple of 2 bytes in the range");
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b61992298ca95..f8bde54ac8a4d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -161,6 +161,11 @@ class UImmAsmOperand<int width, string suffix = "">
: ImmAsmOperand<"U", width, suffix> {
}
+class BareSImmNLsb0AsmOperand<int width>
+ : ImmAsmOperand<"BareS", width, "Lsb0"> {
+ let PredicateMethod = "isBareSimmNLsb0<" # width # ">";
+}
+
class RISCVOp<ValueType vt = XLenVT> : Operand<vt> {
let OperandNamespace = "RISCVOp";
}
@@ -271,8 +276,8 @@ def simm12_no6 : ImmLeaf<XLenVT, [{
return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);}]>;
// A 13-bit signed immediate where the least significant bit is zero.
-def simm13_lsb0 : Operand<OtherVT> {
- let ParserMatchClass = SImmAsmOperand<13, "Lsb0">;
+def bare_simm13_lsb0 : Operand<OtherVT> {
+ let ParserMatchClass = BareSImmNLsb0AsmOperand<13>;
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
@@ -303,7 +308,7 @@ def uimm20_auipc : UImm20OperandMaybeSym {
def uimm20 : RISCVUImmOp<20>;
-def Simm21Lsb0JALAsmOperand : SImmAsmOperand<21, "Lsb0JAL"> {
+def Simm21Lsb0JALAsmOperand : BareSImmNLsb0AsmOperand<21> {
let ParserMethod = "parseJALOffset";
}
@@ -527,7 +532,7 @@ include "RISCVInstrFormatsV.td"
class BranchCC_rri<bits<3> funct3, string opcodestr>
: RVInstB<funct3, OPC_BRANCH, (outs),
- (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
+ (ins GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $rs2, $imm12">,
Sched<[WriteJmp, ReadJmp, ReadJmp]> {
let isBranch = 1;
@@ -959,30 +964,30 @@ def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>;
def : InstAlias<"beqz $rs, $offset",
- (BEQ GPR:$rs, X0, simm13_lsb0:$offset)>;
+ (BEQ GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bnez $rs, $offset",
- (BNE GPR:$rs, X0, simm13_lsb0:$offset)>;
+ (BNE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"blez $rs, $offset",
- (BGE X0, GPR:$rs, simm13_lsb0:$offset)>;
+ (BGE X0, GPR:$rs, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bgez $rs, $offset",
- (BGE GPR:$rs, X0, simm13_lsb0:$offset)>;
+ (BGE GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bltz $rs, $offset",
- (BLT GPR:$rs, X0, simm13_lsb0:$offset)>;
+ (BLT GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
def : InstAlias<"bgtz $rs, $offset",
- (BLT X0, GPR:$rs, simm13_lsb0:$offset)>;
+ (BLT X0, GPR:$rs, bare_simm13_lsb0:$offset)>;
// Always output the canonical mnemonic for the pseudo branch instructions.
// The GNU tools emit the canonical mnemonic for the branch pseudo instructions
// as well (e.g. "bgt" will be recognised by the assembler but never printed by
// objdump). Match this behaviour by setting a zero weight.
def : InstAlias<"bgt $rs, $rt, $offset",
- (BLT GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
+ (BLT GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"ble $rs, $rt, $offset",
- (BGE GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
+ (BGE GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"bgtu $rs, $rt, $offset",
- (BLTU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
+ (BLTU GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"bleu $rs, $rt, $offset",
- (BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>;
+ (BGEU GPR:$rt, GPR:$rs, bare_simm13_lsb0:$offset), 0>;
def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>;
def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>;
@@ -1165,7 +1170,7 @@ def InsnI_Mem : DirectiveInsnI<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
"$opcode, $funct3, $rd, ${imm12}(${rs1})">;
def InsnB : DirectiveInsnB<(outs), (ins uimm7_opcode:$opcode, uimm3:$funct3,
AnyReg:$rs1, AnyReg:$rs2,
- simm13_lsb0:$imm12),
+ bare_simm13_lsb0:$imm12),
"$opcode, $funct3, $rs1, $rs2, $imm12">;
def InsnU : DirectiveInsnU<(outs AnyReg:$rd), (ins uimm7_opcode:$opcode,
uimm20_lui:$imm20),
@@ -1221,11 +1226,11 @@ def : InstAlias<".insn_i $opcode, $funct3, $rd, (${rs1})",
AnyReg:$rs1, 0)>;
def : InstAlias<".insn_b $opcode, $funct3, $rs1, $rs2, $imm12",
(InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
- AnyReg:$rs2, simm13_lsb0:$imm12)>;
+ AnyReg:$rs2, bare_simm13_lsb0:$imm12)>;
// Accept sb as an alias for b.
def : InstAlias<".insn_sb $opcode, $funct3, $rs1, $rs2, $imm12",
(InsnB uimm7_opcode:$opcode, uimm3:$funct3, AnyReg:$rs1,
- AnyReg:$rs2, simm13_lsb0:$imm12)>;
+ AnyReg:$rs2, bare_simm13_lsb0:$imm12)>;
def : InstAlias<".insn_u $opcode, $rd, $imm20",
(InsnU AnyReg:$rd, uimm7_opcode:$opcode, uimm20_lui:$imm20)>;
def : InstAlias<".insn_j $opcode, $rd, $imm20",
@@ -1571,10 +1576,10 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.
multiclass BccPat<CondCode Cond, RVInstB Inst> {
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), GPR:$rs2, Cond, bb:$imm12),
- (Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
+ (Inst GPR:$rs1, GPR:$rs2, bare_simm13_lsb0:$imm12)>;
// Explicitly select 0 to X0. The register coalescer doesn't always do it.
def : Pat<(riscv_brcc (XLenVT GPR:$rs1), 0, Cond, bb:$imm12),
- (Inst GPR:$rs1, (XLenVT X0), simm13_lsb0:$imm12)>;
+ (Inst GPR:$rs1, (XLenVT X0), bare_simm13_lsb0:$imm12)>;
}
class BrccCompressOpt<CondCode Cond, RVInstB Inst>
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 375fe640c6c3d..199d056986dc2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -138,9 +138,9 @@ def uimm8_lsb000 : RISCVOp,
}
// A 9-bit signed immediate where the least significant bit is zero.
-def simm9_lsb0 : Operand<OtherVT>,
- ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
- let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
+def bare_simm9_lsb0 : Operand<OtherVT>,
+ ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
+ let ParserMatchClass = BareSImmNLsb0AsmOperand<9>;
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
@@ -202,9 +202,9 @@ def simm10_lsb0000nonzero : RISCVOp,
}
// A 12-bit signed immediate where the least significant bit is zero.
-def simm12_lsb0 : Operand<XLenVT>,
- ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
- let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
+def bare_simm12_lsb0 : Operand<OtherVT>,
+ ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
+ let ParserMatchClass = BareSImmNLsb0AsmOperand<12>;
let PrintMethod = "printBranchOperand";
let EncoderMethod = "getImmOpValueAsr1";
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
@@ -258,7 +258,7 @@ class CStore_rri<bits<3> funct3, string OpcodeStr,
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class Bcz<bits<3> funct3, string OpcodeStr>
- : RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, simm9_lsb0:$imm),
+ : RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),
OpcodeStr, "$rs1, $imm"> {
let isBranch = 1;
let isTerminator = 1;
@@ -417,7 +417,7 @@ def PseudoC_ADDI_NOP : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, immzero:$imm),
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
DecoderNamespace = "RV32Only", Defs = [X1],
Predicates = [HasStdExtCOrZca, IsRV32] in
-def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
+def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
"c.jal", "$offset">, Sched<[WriteJal]>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
@@ -486,7 +486,7 @@ def C_ADDW : CA_ALU<0b100111, 0b01, "c.addw">,
}
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
+def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
"c.j", "$offset">, Sched<[WriteJmp]> {
let isBranch = 1;
let isTerminator=1;
@@ -793,11 +793,11 @@ def InsnCA : DirectiveInsnCA<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
"$opcode, $funct6, $funct2, $rd, $rs2">;
def InsnCB : DirectiveInsnCB<(outs), (ins uimm2_opcode:$opcode, uimm3:$funct3,
AnyRegC:$rs1,
- simm9_lsb0:$imm8),
+ bare_simm9_lsb0:$imm8),
"$opcode, $funct3, $rs1, $imm8">;
def InsnCJ : DirectiveInsnCJ<(outs), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
- simm12_lsb0:$imm11),
+ bare_simm12_lsb0:$imm11),
"$opcode, $funct3, $imm11">;
def Insn16 : RVInst16<(outs), (ins uimm16:$value), "", "", [], InstFormatOther> {
bits<16> value;
@@ -841,9 +841,9 @@ def : InstAlias<".insn_ca $opcode, $funct6, $funct2, $rd, $rs2",
uimm2:$funct2, AnyRegC:$rs2)>;
def : InstAlias<".insn_cb $opcode, $funct3, $rs1, $imm8",
(InsnCB uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs1,
- simm9_lsb0:$imm8)>;
+ bare_simm9_lsb0:$imm8)>;
def : InstAlias<".insn_cj $opcode, $funct3, $imm11",
- (InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, simm12_lsb0:$imm11)>;
+ (InsnCJ uimm2_opcode:$opcode, uimm3:$funct3, bare_simm12_lsb0:$imm11)>;
}
//===----------------------------------------------------------------------===/i
@@ -915,8 +915,8 @@ def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
} // Predicates = [HasStdExtCOrZca]
let Predicates = [HasStdExtCOrZca, IsRV32] in {
-def : CompressPat<(JAL X1, simm12_lsb0:$offset),
- (C_JAL simm12_lsb0:$offset)>;
+def : CompressPat<(JAL X1, bare_simm12_lsb0:$offset),
+ (C_JAL bare_simm12_lsb0:$offset)>;
} // Predicates = [HasStdExtCOrZca, IsRV32]
let Predicates = [HasStdExtCOrZca, IsRV64] in {
@@ -970,18 +970,18 @@ def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
} // Predicates = [HasStdExtCOrZca, IsRV64]
let Predicates = [HasStdExtCOrZca] in {
-def : CompressPat<(JAL X0, simm12_lsb0:$offset),
- (C_J simm12_lsb0:$offset)>;
-def : CompressPat<(BEQ GPRC:$rs1, X0, simm9_lsb0:$imm),
- (C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(JAL X0, bare_simm12_lsb0:$offset),
+ (C_J bare_simm12_lsb0:$offset)>;
+def : CompressPat<(BEQ GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
+ (C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
let isCompressOnly = true in
-def : CompressPat<(BEQ X0, GPRC:$rs1, simm9_lsb0:$imm),
- (C_BEQZ GPRC:$rs1, simm9_lsb0:$imm)>;
-def : CompressPat<(BNE GPRC:$rs1, X0, simm9_lsb0:$imm),
- (C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(BEQ X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
+ (C_BEQZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
+def : CompressPat<(BNE GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
+ (C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
let isCompressOnly = true in
-def : CompressPat<(BNE X0, GPRC:$rs1, simm9_lsb0:$imm),
- (C_BNEZ GPRC:$rs1, simm9_lsb0:$imm)>;
+def : CompressPat<(BNE X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
+ (C_BNEZ GPRC:$rs1, bare_simm9_lsb0:$imm)>;
} // Predicates = [HasStdExtCOrZca]
// Quadrant 2
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index c14f8bb9fe41c..b5df7b54fc9f1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -590,10 +590,10 @@ let Predicates = [HasVendorXCVsimd, IsRV32] in {
let Predicates = [HasVendorXCVbi, IsRV32] in {
// Immediate branching operations
def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
- (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+ (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
"cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
- (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+ (ins GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12),
"cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
}
@@ -793,9 +793,9 @@ let Predicates = [HasVendorXCValu, IsRV32], AddedComplexity = 1 in {
let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETEQ, bb:$imm12),
- (CV_BEQIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
+ (CV_BEQIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
- (CV_BNEIMM GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12)>;
+ (CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
let usesCustomInserter = 1 in
def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 86c521010add4..b3ac9ec7cff41 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -314,7 +314,7 @@ class QCIRVInst16CI_RS1<bits<5> funct5, string OpcodeStr>
class QCIBranchInst_rii<bits<3> funct3, DAGOperand InTyImm5, string opcodestr>
: RVInstB<funct3, OPC_CUSTOM_3, (outs),
- (ins GPRNoX0:$rs1, InTyImm5:$rs2, simm13_lsb0:$imm12),
+ (ins GPRNoX0:$rs1, InTyImm5:$rs2, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $rs2, $imm12"> {
let isBranch = 1;
let isTerminator = 1;
@@ -324,7 +324,8 @@ class QCIBranchInst_rii<bits<3> funct3, DAGOperand InTyImm5, string opcodestr>
}
class QCIBranchInst48_rii<bits<5> funct5, DAGOperand InTyImm16, string opcodestr>
- : RVInst48<(outs), (ins GPRNoX0:$rs1, InTyImm16:$imm16, simm13_lsb0:$imm12),
+ : RVInst48<(outs),
+ (ins GPRNoX0:$rs1, InTyImm16:$imm16, bare_simm13_lsb0:$imm12),
opcodestr, "$rs1, $imm16, $imm12", [], InstFormatOther> {
bits<5> rs1;
bits<16> imm16;
More information about the llvm-commits
mailing list