[llvm] a983c3b - [TableGen] Make more use of CodeGenRegisterClass::EnumValue. NFC. (#132749)
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Fri Mar 28 08:54:57 PDT 2025
Author: Jay Foad
Date: 2025-03-28T15:54:53Z
New Revision: a983c3b209bf6602c0687251647535c7fa43a17a
URL: https://github.com/llvm/llvm-project/commit/a983c3b209bf6602c0687251647535c7fa43a17a
DIFF: https://github.com/llvm/llvm-project/commit/a983c3b209bf6602c0687251647535c7fa43a17a.diff
LOG: [TableGen] Make more use of CodeGenRegisterClass::EnumValue. NFC. (#132749)
Added:
Modified:
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 9c2681469116e..7105ced26be1c 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2106,9 +2106,7 @@ void CodeGenRegBank::computeRegUnitSets() {
// For each register class, list the UnitSets that are supersets.
RegClassUnitSets.resize(RegClasses.size());
- int RCIdx = -1;
for (auto &RC : RegClasses) {
- ++RCIdx;
if (!RC.Allocatable)
continue;
@@ -2130,12 +2128,13 @@ void CodeGenRegBank::computeRegUnitSets() {
++USIdx) {
if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
LLVM_DEBUG(dbgs() << " " << USIdx);
- RegClassUnitSets[RCIdx].push_back(USIdx);
+ RegClassUnitSets[RC.EnumValue].push_back(USIdx);
}
}
LLVM_DEBUG(dbgs() << "\n");
- assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) &&
- "missing unit set for regclass");
+ assert(
+ (!RegClassUnitSets[RC.EnumValue].empty() || !RC.GeneratePressureSet) &&
+ "missing unit set for regclass");
}
// For each register unit, ensure that we have the list of UnitSets that
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