[llvm] [AMDGPU][True16][CodeGen] remove v2i16 from srl pattern (PR #133458)

[Brox Chen via llvm-commits]

https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/133458

remove v2i16 from srl true16 pattern since 16bit right shift on v2i16 should not be applied with this pattern

>From 89acb032d66c5d0f5bd13fad897eaadbad93b6e7 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Fri, 28 Mar 2025 11:48:48 -0400
Subject: [PATCH] remove v2i16 from srl pattern

---
 llvm/lib/Target/AMDGPU/SIInstructions.td | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 95797e96aa77e..9051db0c01ed1 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2426,9 +2426,8 @@ def : GCNPat <(i1 imm:$imm),
 }
 
 let True16Predicate = UseRealTrue16Insts in
-foreach vt = [i32, v2i16] in
 def : GCNPat <
-  (vt (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
+  (i32 (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
   (REG_SEQUENCE VGPR_32, (i16 (EXTRACT_SUBREG $src, hi16)), lo16, (V_MOV_B16_t16_e64 0, (i16 0x0000), 0), hi16)
 >;