[llvm] [AMDGPU] SIPeepholeSDWA: Add REG_SEQUENCE support (PR #133087)

[Matt Arsenault via llvm-commits]

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@@ -278,11 +281,16 @@ static void copyRegOperand(MachineOperand &To, const MachineOperand &From) {
   }
 }
 
+static bool isSameReg(const MachineOperand &Op, Register Reg) {
+  return Op.isReg() && Op.getReg() == Reg;
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arsenm wrote:

isReg can never be false for the copy-like contexts you're looking at 

https://github.com/llvm/llvm-project/pull/133087