[llvm] AMDGPU: Convert vector 64-bit shl to 32-bit if shift amt >= 32 (PR #132964)

[via llvm-commits]

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@@ -4116,9 +4119,21 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDValue NewShift =
       DAG.getNode(ISD::SHL, SL, TargetType, Lo, ShiftAmt, N->getFlags());
 
-  const SDValue Zero = DAG.getConstant(0, SL, TargetType);
-
-  SDValue Vec = DAG.getBuildVector(TargetVecPairType, SL, {Zero, NewShift});
+  const SDValue Zero = DAG.getConstant(0, SL, TargetScalarType);
+  SDValue Vec;
+
+  if (VT.isVector()) {
+    EVT ConcatType = TargetType.getDoubleNumVectorElementsVT(*DAG.getContext());
+    unsigned NElts = TargetType.getVectorNumElements();
+    SmallVector<SDValue, 8> Ops;
+    DAG.ExtractVectorElements(NewShift, Ops, 0, NElts);
+    for (unsigned I = 0; I != NElts; ++I)
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LU-JOHN wrote:

Re-coded with array indexing and new renamed vectors.  Hopefully this makes comment unnecessary.

https://github.com/llvm/llvm-project/pull/132964