[llvm] [RISCV] Add OR/XOR/SUB to RISCVInstrInfo::isCopyInstrImpl (PR #132002)

[Alex Bradbury via llvm-commits]

asb wrote:

I explored some of the things mentioned here in review:
* I don't see any left/right shifts with 0. I do however see left/right shifts of the `zero` register. I've got a pretty comprehensive dump of 'odd' scalar instructions in llvm-test-suite binaries (either deletable as nops, or an inefficient encoding or some other operation that should be replaced). I'll make a tracking issue summarising this.
* I won't add the or with equal reg args case for the time being. The script I have will flag if I start seeing it in the test suite / spec, and perhaps it becomes clear what coverage we want and where when tracking down other unwanted instructions.
* I don't believe this is a canonicalisation problem. I've sampled a few affected cases, made an llvm-reduced test case and looked at the log. I've confirmed it's the same flow that motivated the recent extension to MachineCopyPropagation to catch these nops. For one I just looked through the tail duplicator kicks in, one of the branches ends up with a COPY of x0 feeding into the `sub` while the other has a semantically sensible `sub`. MachineCopyPropagation is run just after it in the pass pipeline, and once we fill in these missing gaps it succeeds in its goal of cleaning up the tail duplicator output.

I'll go ahead and merge this now and follow-up on other observed oddities with PRs / issues.

https://github.com/llvm/llvm-project/pull/132002