[llvm] [AArch64] Custom lower v4i8 subreg extract. (PR #133438)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 28 05:44:04 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
A v4i8 extract will usually be scalarized. This prevents that during lowering, converting it to an anyext and larger v4i16 subvector extract. There are a few minor regressions that are fixed up in the last patch in this commit.
The fold in DAGCombine was not handling the extended BUILDVECTORs that we see when i8/i16 are not legal types. Using isConstOrConstSplat(N1, false, true) allows it to match truncated constants. The other changes in visitAND are to make sure that truncated values in N1C are treated correctly, the fold we are mostly interested in is:
```
if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C &&
ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
```
I couldn't find any other places where this triggered, as buildvectors are usually optimized before type legalization.
This also currently includes #<!-- -->133433.
---
Patch is 82.42 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/133438.diff
25 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+3-2)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+13-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+17)
- (modified) llvm/test/CodeGen/AArch64/aarch64-load-ext.ll (+3-6)
- (modified) llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll (+8-8)
- (modified) llvm/test/CodeGen/AArch64/add.ll (+1-3)
- (modified) llvm/test/CodeGen/AArch64/andorxor.ll (+9-9)
- (modified) llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/bitcast.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/ctlz.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/ctpop.ll (+1-2)
- (modified) llvm/test/CodeGen/AArch64/extbinopload.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/extract-subvec-combine.ll (+13-6)
- (modified) llvm/test/CodeGen/AArch64/insert-subvector.ll (+1-1)
- (modified) llvm/test/CodeGen/AArch64/itofp.ll (+286-510)
- (modified) llvm/test/CodeGen/AArch64/load.ll (+4-3)
- (modified) llvm/test/CodeGen/AArch64/mul.ll (+2-4)
- (modified) llvm/test/CodeGen/AArch64/neon-bitcast.ll (+2-3)
- (modified) llvm/test/CodeGen/AArch64/sub.ll (+1-3)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll (+1-3)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll (+8-10)
- (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll (+7-12)
- (modified) llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll (+9-16)
- (modified) llvm/test/CodeGen/AArch64/vector-fcvt.ll (+102-198)
- (modified) llvm/test/CodeGen/AArch64/zext.ll (+1-1)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2fd744391b917..c39ac138b3ace 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7166,7 +7166,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// if (and x, c) is known to be zero, return 0
unsigned BitWidth = VT.getScalarSizeInBits();
- ConstantSDNode *N1C = isConstOrConstSplat(N1);
+ ConstantSDNode *N1C = isConstOrConstSplat(N1, false, true);
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(BitWidth)))
return DAG.getConstant(0, DL, VT);
@@ -7205,7 +7205,8 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0Op0);
// fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) if profitable.
- if (N1C->getAPIntValue().countLeadingZeros() >= (BitWidth - SrcBitWidth) &&
+ APInt N1APInt = N1C->getAPIntValue().trunc(VT.getScalarSizeInBits());
+ if (N1APInt.countLeadingZeros() >= (BitWidth - SrcBitWidth) &&
TLI.isTruncateFree(VT, SrcVT) && TLI.isZExtFree(SrcVT, VT) &&
TLI.isTypeDesirableForOp(ISD::AND, SrcVT) &&
TLI.isNarrowingProfitable(N, VT, SrcVT))
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 1c8e3afdfd718..2ef1d9a6bff23 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1426,6 +1426,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::v2i16, Custom);
setOperationAction(ISD::BITCAST, MVT::v4i8, Custom);
+ setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i8, Custom);
+
setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Custom);
@@ -27309,12 +27311,22 @@ void AArch64TargetLowering::ReplaceExtractSubVectorResults(
SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
SDValue In = N->getOperand(0);
EVT InVT = In.getValueType();
+ SDLoc DL(N);
+
+ if (N->getValueType(0) == MVT::v4i8 &&
+ N->getOperand(0).getValueType() == MVT::v8i8 &&
+ (N->getConstantOperandVal(1) == 0 || N->getConstantOperandVal(1) == 4)) {
+ SDValue Ext =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::v8i16, N->getOperand(0));
+ Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Ext,
+ N->getOperand(1));
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::v4i8, Ext));
+ }
// Common code will handle these just fine.
if (!InVT.isScalableVector() || !InVT.isInteger())
return;
- SDLoc DL(N);
EVT VT = N->getValueType(0);
// The following checks bail if this is not a halving operation.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 6c61e3a613f6f..f291589e04c6b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -6751,6 +6751,23 @@ def : Pat<(v4i32 (concat_vectors
(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Vm), (i32 32)))))),
(UZP2v4i32 V128:$Vn, V128:$Vm)>;
+// extract_subvec(anyext) can use zip. Check for one use on the anyext, otherwise
+// the extract_subvector can be free.
+let HasOneUse = 1 in
+def anyext_oneuse: PatFrag<(ops node:$src0), (anyext $src0)>;
+def : Pat<(v4i16 (extract_subvector (v8i16 (anyext_oneuse (v8i8 V64:$Vn))), (i64 0))),
+ (ZIP1v8i8 V64:$Vn, V64:$Vn)>;
+def : Pat<(v2i32 (extract_subvector (v4i32 (anyext_oneuse (v4i16 V64:$Vn))), (i64 0))),
+ (ZIP1v4i16 V64:$Vn, V64:$Vn)>;
+def : Pat<(v1i64 (extract_subvector (v2i64 (anyext_oneuse (v2i32 V64:$Vn))), (i64 0))),
+ (ZIP1v2i32 V64:$Vn, V64:$Vn)>;
+def : Pat<(v4i16 (extract_subvector (v8i16 (anyext_oneuse (v8i8 V64:$Vn))), (i64 4))),
+ (ZIP2v8i8 V64:$Vn, V64:$Vn)>;
+def : Pat<(v2i32 (extract_subvector (v4i32 (anyext_oneuse (v4i16 V64:$Vn))), (i64 2))),
+ (ZIP2v4i16 V64:$Vn, V64:$Vn)>;
+def : Pat<(v1i64 (extract_subvector (v2i64 (anyext_oneuse (v2i32 V64:$Vn))), (i64 1))),
+ (ZIP2v2i32 V64:$Vn, V64:$Vn)>;
+
//----------------------------------------------------------------------------
// AdvSIMD TBL/TBX instructions
//----------------------------------------------------------------------------
diff --git a/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
index 317feb5ad9ad0..1818307be2e10 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
@@ -273,18 +273,15 @@ define <3 x i16> @fsext_v3i16(ptr %a) {
; CHECK-LE-LABEL: fsext_v3i16:
; CHECK-LE: // %bb.0:
; CHECK-LE-NEXT: ldr s0, [x0]
-; CHECK-LE-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-LE-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-LE-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-LE-NEXT: sshll v0.8h, v0.8b, #0
+; CHECK-LE-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: fsext_v3i16:
; CHECK-BE: // %bb.0:
; CHECK-BE-NEXT: ldr s0, [x0]
; CHECK-BE-NEXT: rev32 v0.8b, v0.8b
-; CHECK-BE-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-BE-NEXT: shl v0.4h, v0.4h, #8
-; CHECK-BE-NEXT: sshr v0.4h, v0.4h, #8
+; CHECK-BE-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-BE-NEXT: rev64 v0.4h, v0.4h
; CHECK-BE-NEXT: ret
%x = load <3 x i8>, ptr %a
diff --git a/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll b/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
index 91eda8d552397..f37767291ca14 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-neon-vector-insert-uaddlv.ll
@@ -281,8 +281,8 @@ define void @insert_vec_v16i8_uaddlv_from_v8i8(ptr %0) {
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: uaddlv.8b h1, v0
; CHECK-NEXT: stp q0, q0, [x0, #32]
-; CHECK-NEXT: mov.h v2[0], v1[0]
-; CHECK-NEXT: bic.4h v2, #255, lsl #8
+; CHECK-NEXT: mov.b v2[0], v1[0]
+; CHECK-NEXT: ushll.8h v2, v2, #0
; CHECK-NEXT: ushll.4s v2, v2, #0
; CHECK-NEXT: ucvtf.4s v2, v2
; CHECK-NEXT: stp q2, q0, [x0]
@@ -303,8 +303,8 @@ define void @insert_vec_v8i8_uaddlv_from_v8i8(ptr %0) {
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: stp xzr, xzr, [x0, #16]
; CHECK-NEXT: uaddlv.8b h1, v0
-; CHECK-NEXT: mov.h v0[0], v1[0]
-; CHECK-NEXT: bic.4h v0, #7, lsl #8
+; CHECK-NEXT: mov.b v0[0], v1[0]
+; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: ushll.4s v0, v0, #0
; CHECK-NEXT: ucvtf.4s v0, v0
; CHECK-NEXT: str q0, [x0]
@@ -433,8 +433,8 @@ define void @insert_vec_v8i8_uaddlv_from_v4i32(ptr %0) {
; CHECK-NEXT: movi.2d v1, #0000000000000000
; CHECK-NEXT: stp xzr, xzr, [x0, #16]
; CHECK-NEXT: uaddlv.4s d0, v0
-; CHECK-NEXT: mov.h v1[0], v0[0]
-; CHECK-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-NEXT: mov.b v1[0], v0[0]
+; CHECK-NEXT: ushll.8h v1, v1, #0
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: str q1, [x0]
@@ -457,8 +457,8 @@ define void @insert_vec_v16i8_uaddlv_from_v4i32(ptr %0) {
; CHECK-NEXT: movi.2d v2, #0000000000000000
; CHECK-NEXT: uaddlv.4s d0, v0
; CHECK-NEXT: stp q2, q2, [x0, #32]
-; CHECK-NEXT: mov.h v1[0], v0[0]
-; CHECK-NEXT: bic.4h v1, #255, lsl #8
+; CHECK-NEXT: mov.b v1[0], v0[0]
+; CHECK-NEXT: ushll.8h v1, v1, #0
; CHECK-NEXT: ushll.4s v1, v1, #0
; CHECK-NEXT: ucvtf.4s v1, v1
; CHECK-NEXT: stp q1, q2, [x0]
diff --git a/llvm/test/CodeGen/AArch64/add.ll b/llvm/test/CodeGen/AArch64/add.ll
index fc0ba336b21cc..4ecd17ae3b9af 100644
--- a/llvm/test/CodeGen/AArch64/add.ll
+++ b/llvm/test/CodeGen/AArch64/add.ll
@@ -97,9 +97,7 @@ define void @v3i8(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b
-; CHECK-SD-NEXT: add v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: uaddl v0.8h, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: umov w8, v0.h[2]
; CHECK-SD-NEXT: str s1, [sp, #12]
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index 24f2549cce785..439351cf0d2ac 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -292,7 +292,7 @@ define void @and_v3i8(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: umov w8, v0.h[2]
@@ -340,7 +340,7 @@ define void @or_v3i8(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: umov w8, v0.h[2]
@@ -388,7 +388,7 @@ define void @xor_v3i8(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b
+; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: umov w8, v0.h[2]
@@ -433,8 +433,8 @@ define void @and_v4i8(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: str s0, [x0]
@@ -482,8 +482,8 @@ define void @or_v4i8(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: str s0, [x0]
@@ -531,8 +531,8 @@ define void @xor_v4i8(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-SD-NEXT: str s0, [x0]
diff --git a/llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll b/llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
index 864ddc2967c18..90fa294505c84 100644
--- a/llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
@@ -6,8 +6,7 @@
define <2 x i16> @bitcast_v2i16_v2f16(<2 x half> %x) {
; CHECK-LABEL: bitcast_v2i16_v2f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%y = bitcast <2 x half> %x to <2 x i16>
ret <2 x i16> %y
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index d9199ce2c79de..d54cc4adb81b3 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -125,8 +125,7 @@ define <2 x i16> @bitcast_i32_v2i16(i32 %a, i32 %b){
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: add w8, w0, w1
; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: bitcast_i32_v2i16:
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index 742433c50d390..facc15ef15e8b 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -42,10 +42,9 @@ define void @v3i8(ptr %p1) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
-; CHECK-SD-NEXT: movi v0.4h, #8
; CHECK-SD-NEXT: ldr s1, [x0]
-; CHECK-SD-NEXT: zip1 v1.8b, v1.8b, v0.8b
-; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8
+; CHECK-SD-NEXT: movi v0.4h, #8
+; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-SD-NEXT: clz v1.4h, v1.4h
; CHECK-SD-NEXT: sub v0.4h, v1.4h, v0.4h
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index c7c378d3e67cd..edb1d55a15733 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -43,8 +43,7 @@ define void @v3i8(ptr %p1) {
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: ldr s0, [x0]
-; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-SD-NEXT: cnt v0.8b, v0.8b
; CHECK-SD-NEXT: uaddlp v0.4h, v0.8b
; CHECK-SD-NEXT: uzp1 v1.8b, v0.8b, v0.8b
diff --git a/llvm/test/CodeGen/AArch64/extbinopload.ll b/llvm/test/CodeGen/AArch64/extbinopload.ll
index 72f4d58a425e7..47de51c6cdc0d 100644
--- a/llvm/test/CodeGen/AArch64/extbinopload.ll
+++ b/llvm/test/CodeGen/AArch64/extbinopload.ll
@@ -649,7 +649,7 @@ define <16 x i32> @extrause_load(ptr %p, ptr %q, ptr %r, ptr %s, ptr %z) {
; CHECK-NEXT: add x8, x3, #8
; CHECK-NEXT: add x11, x1, #12
; CHECK-NEXT: str s1, [x4]
-; CHECK-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-NEXT: ldr s0, [x2]
; CHECK-NEXT: ushll v2.8h, v0.8b, #0
; CHECK-NEXT: umov w9, v2.h[0]
@@ -659,7 +659,7 @@ define <16 x i32> @extrause_load(ptr %p, ptr %q, ptr %r, ptr %s, ptr %z) {
; CHECK-NEXT: mov v0.b[9], w10
; CHECK-NEXT: umov w10, v2.h[3]
; CHECK-NEXT: ldr s2, [x1]
-; CHECK-NEXT: ushll v2.8h, v2.8b, #0
+; CHECK-NEXT: zip1 v2.8b, v2.8b, v2.8b
; CHECK-NEXT: mov v0.b[10], w9
; CHECK-NEXT: add x9, x1, #4
; CHECK-NEXT: mov v1.d[1], v2.d[0]
@@ -1366,11 +1366,11 @@ define <4 x i32> @atomic(ptr %p) {
; CHECK-LABEL: atomic:
; CHECK: // %bb.0:
; CHECK-NEXT: ldar w8, [x0]
-; CHECK-NEXT: movi v0.2d, #0x0000ff000000ff
; CHECK-NEXT: ldr s1, [x0, #4]
+; CHECK-NEXT: movi v0.2d, #0x0000ff000000ff
; CHECK-NEXT: fmov s2, w8
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-NEXT: zip1 v2.8b, v2.8b, v0.8b
+; CHECK-NEXT: zip1 v2.8b, v2.8b, v2.8b
; CHECK-NEXT: ushll v1.4s, v1.4h, #3
; CHECK-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
diff --git a/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll b/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
index 75d55773b3681..368103bf2f2fe 100644
--- a/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
+++ b/llvm/test/CodeGen/AArch64/extract-subvec-combine.ll
@@ -104,12 +104,19 @@ define <2 x i32> @sext_extract_zext_idx0(<4 x i16> %vec) nounwind {
; Negative test, combine should not fire if sign extension is for a different width.
define <2 x i32> @sext_extract_zext_idx0_negtest(<4 x i16> %vec) nounwind {
-; CHECK-LABEL: sext_extract_zext_idx0_negtest:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: shl v0.2s, v0.2s, #17
-; CHECK-NEXT: sshr v0.2s, v0.2s, #17
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sext_extract_zext_idx0_negtest:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: shl v0.2s, v0.2s, #17
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sext_extract_zext_idx0_negtest:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-GI-NEXT: shl v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #17
+; CHECK-GI-NEXT: ret
%zext = zext <4 x i16> %vec to <4 x i32>
%extract = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %zext, i64 0)
%sext_inreg_step0 = shl <2 x i32> %extract, <i32 17, i32 17>
diff --git a/llvm/test/CodeGen/AArch64/insert-subvector.ll b/llvm/test/CodeGen/AArch64/insert-subvector.ll
index 6828fa9f1508c..a91ff58d9e99a 100644
--- a/llvm/test/CodeGen/AArch64/insert-subvector.ll
+++ b/llvm/test/CodeGen/AArch64/insert-subvector.ll
@@ -465,7 +465,7 @@ define <4 x i8> @load_v4i8_2_2(float %tmp, <4 x i8> %b, ptr %a) {
; CHECK-LABEL: load_v4i8_2_2:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0]
-; CHECK-NEXT: zip1 v2.8b, v0.8b, v0.8b
+; CHECK-NEXT: ushll v2.8h, v0.8b, #0
; CHECK-NEXT: fmov d0, d1
; CHECK-NEXT: mov v0.s[1], v2.s[0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
diff --git a/llvm/test/CodeGen/AArch64/itofp.ll b/llvm/test/CodeGen/AArch64/itofp.ll
index 07957c117868d..80a7d47c063e4 100644
--- a/llvm/test/CodeGen/AArch64/itofp.ll
+++ b/llvm/test/CodeGen/AArch64/itofp.ll
@@ -3442,39 +3442,27 @@ entry:
define <8 x double> @stofp_v8i8_v8f64(<8 x i8> %a) {
; CHECK-SD-LABEL: stofp_v8i8_v8f64:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: umov w8, v0.b[0]
-; CHECK-SD-NEXT: umov w9, v0.b[2]
-; CHECK-SD-NEXT: umov w11, v0.b[4]
-; CHECK-SD-NEXT: umov w12, v0.b[6]
-; CHECK-SD-NEXT: umov w10, v0.b[1]
-; CHECK-SD-NEXT: umov w13, v0.b[3]
-; CHECK-SD-NEXT: umov w14, v0.b[5]
-; CHECK-SD-NEXT: umov w15, v0.b[7]
-; CHECK-SD-NEXT: fmov s0, w8
-; CHECK-SD-NEXT: fmov s1, w9
-; CHECK-SD-NEXT: fmov s2, w11
-; CHECK-SD-NEXT: fmov s3, w12
-; CHECK-SD-NEXT: mov v0.s[1], w10
-; CHECK-SD-NEXT: mov v1.s[1], w13
-; CHECK-SD-NEXT: mov v2.s[1], w14
-; CHECK-SD-NEXT: mov v3.s[1], w15
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
+; CHECK-SD-NEXT: ushll2 v1.4s, v0.8h, #0
+; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
+; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
+; CHECK-SD-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24
; CHECK-SD-NEXT: shl v1.2s, v1.2s, #24
+; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-SD-NEXT: shl v2.2s, v2.2s, #24
; CHECK-SD-NEXT: shl v3.2s, v3.2s, #24
-; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-SD-NEXT: sshr v1.2s, v1.2s, #24
+; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-SD-NEXT: sshr v2.2s, v2.2s, #24
; CHECK-SD-NEXT: sshr v3.2s, v3.2s, #24
-; CHECK-SD-NEXT: sshll v0.2d, v0.2s, #0
; CHECK-SD-NEXT: sshll v1.2d, v1.2s, #0
-; CHECK-SD-NEXT: sshll v2.2d, v2.2s, #0
-; CHECK-SD-NEXT: sshll v3.2d, v3.2s, #0
; CHECK-SD-NEXT: scvtf v0.2d, v0.2d
-; CHECK-SD-NEXT: scvtf v1.2d, v1.2d
-; CHECK-SD-NEXT: scvtf v2.2d, v2.2d
-; CHECK-SD-NEXT: scvtf v3.2d, v3.2d
+; CHECK-SD-NEXT: sshll v4.2d, v2.2s, #0
+; CHECK-SD-NEXT: sshll v5.2d, v3.2s, #0
+; CHECK-SD-NEXT: scvtf v2.2d, v1.2d
+; CHECK-SD-NEXT: scvtf v3.2d, v4.2d
+; CHECK-SD-NEXT: scvtf v1.2d, v5.2d
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: stofp_v8i8_v8f64:
@@ -3499,36 +3487,24 @@ entry:
define <8 x double> @utofp_v8i8_v8f64(<8 x i8> %a) {
; CHECK-SD-LABEL: utofp_v8i8_v8f64:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: umov w8, v0.b[0]
-; CHECK-SD-NEXT: umov w9, v0.b[2]
-; CHECK-SD-NEXT: umov w11, v0.b[4]
-; CHECK-SD-NEXT: umov w12, v0.b[6]
-; CHECK-SD-NEXT: umov w10, v0.b[1]
-; CHECK-SD-NEXT: umov w13, v0.b[3]
-; CHECK-SD-NEXT: umov w14, v0.b[5]
-; CHECK-SD-NEXT: umov w15, v0.b[7]
+; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-SD-NEXT: movi d1, #0x0000ff000000ff
-; CHECK-S...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/133438
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