[llvm] [Analysis] Make LocationSize conversion from uint64_t explicit (PR #133342)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 27 21:07:02 PDT 2025
https://github.com/preames updated https://github.com/llvm/llvm-project/pull/133342
>From 88f4db6ef11b3dfcb985b9ce6710da5e5b2cd718 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Thu, 27 Mar 2025 12:10:29 -0700
Subject: [PATCH 1/2] [Analysis] Make LocationSize conversion from uint64_t
explicit
This change makes the uint64_t constructor on LocationSize explicit
preventing implicit conversion, and fixes up the using APIs to adapt
to the change. Note that I'm adding a couple of explicit conversion
points on routines where passing in a fixed offset as an integer
seems likely to have well understood semantics.
We had an unfortunate case which arose if you tried to pass a TypeSize
value to a parameter of LocationSize type. We'd find the implicit
conversion path through TypeSize -> uint64_t -> LocationSize which
works just fine for fixed values, but looses information and fails
assertios if the TypeSize was scalable. This change breaks the
first link in that implicit conversion chain since that seemed to
be the easier one.
---
llvm/include/llvm/Analysis/MemoryLocation.h | 22 +++++++++++++++----
llvm/include/llvm/CodeGen/MachineFunction.h | 19 ++++++++++++++++
llvm/include/llvm/CodeGen/SelectionDAG.h | 6 +++--
llvm/lib/CodeGen/MachineScheduler.cpp | 2 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 6 ++---
llvm/lib/CodeGen/TargetInstrInfo.cpp | 2 +-
.../lib/Target/AMDGPU/SIInsertHardClauses.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 20 +++++++++--------
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 6 ++---
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 4 ++--
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 9 ++++----
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 6 +++--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 ++---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 ++-
llvm/lib/Target/X86/X86InstrInfo.cpp | 4 ++--
.../Target/RISCV/RISCVInstrInfoTest.cpp | 2 +-
16 files changed, 80 insertions(+), 39 deletions(-)
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h
index ea29e21bd18f2..345dbe0cf0e50 100644
--- a/llvm/include/llvm/Analysis/MemoryLocation.h
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h
@@ -102,7 +102,7 @@ class LocationSize {
//
// Since the overwhelming majority of users of this provide precise values,
// this assumes the provided value is precise.
- constexpr LocationSize(uint64_t Raw)
+ explicit constexpr LocationSize(uint64_t Raw)
: Value(Raw > MaxValue ? AfterPointer : Raw) {}
// Create non-scalable LocationSize
static LocationSize precise(uint64_t Value) {
@@ -189,14 +189,16 @@ class LocationSize {
bool operator==(const LocationSize &Other) const {
return Value == Other.Value;
}
-
bool operator==(const TypeSize &Other) const {
- return hasValue() && getValue() == Other;
+ return (*this == LocationSize::precise(Other));
+ }
+ bool operator==(const uint64_t &Other) const {
+ return (*this == LocationSize::precise(Other));
}
bool operator!=(const LocationSize &Other) const { return !(*this == Other); }
-
bool operator!=(const TypeSize &Other) const { return !(*this == Other); }
+ bool operator!=(const uint64_t &Other) const { return !(*this == Other); }
// Ordering operators are not provided, since it's unclear if there's only one
// reasonable way to compare:
@@ -301,6 +303,12 @@ class MemoryLocation {
explicit MemoryLocation(const Value *Ptr, LocationSize Size,
const AAMDNodes &AATags = AAMDNodes())
: Ptr(Ptr), Size(Size), AATags(AATags) {}
+ explicit MemoryLocation(const Value *Ptr, TypeSize Size,
+ const AAMDNodes &AATags = AAMDNodes())
+ : Ptr(Ptr), Size(LocationSize::precise(Size)), AATags(AATags) {}
+ explicit MemoryLocation(const Value *Ptr, uint64_t Size,
+ const AAMDNodes &AATags = AAMDNodes())
+ : Ptr(Ptr), Size(LocationSize::precise(Size)), AATags(AATags) {}
MemoryLocation getWithNewPtr(const Value *NewPtr) const {
MemoryLocation Copy(*this);
@@ -313,6 +321,12 @@ class MemoryLocation {
Copy.Size = NewSize;
return Copy;
}
+ MemoryLocation getWithNewSize(uint64_t NewSize) const {
+ return getWithNewSize(LocationSize::precise(NewSize));
+ }
+ MemoryLocation getWithNewSize(TypeSize NewSize) const {
+ return getWithNewSize(LocationSize::precise(NewSize));
+ }
MemoryLocation getWithoutAATags() const {
MemoryLocation Copy(*this);
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 429dd54de33c2..30d414f0829e5 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1072,6 +1072,16 @@ class LLVM_ABI MachineFunction {
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
+ MachineMemOperand *getMachineMemOperand(
+ MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, uint64_t Size,
+ Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
+ const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
+ AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
+ AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic) {
+ return getMachineMemOperand(PtrInfo, F, LocationSize::precise(Size),
+ BaseAlignment, AAInfo, Ranges, SSID, Ordering,
+ FailureOrdering);
+ }
MachineMemOperand *getMachineMemOperand(
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize Size,
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
@@ -1098,6 +1108,10 @@ class LLVM_ABI MachineFunction {
? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue())
: LLT::scalar(8 * Size.getValue().getKnownMinValue()));
}
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ int64_t Offset, uint64_t Size) {
+ return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
+ }
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
int64_t Offset, TypeSize Size) {
return getMachineMemOperand(MMO, Offset, LocationSize::precise(Size));
@@ -1113,6 +1127,11 @@ class LLVM_ABI MachineFunction {
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
const MachinePointerInfo &PtrInfo,
LLT Ty);
+ MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
+ const MachinePointerInfo &PtrInfo,
+ uint64_t Size) {
+ return getMachineMemOperand(MMO, PtrInfo, LocationSize::precise(Size));
+ }
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
const MachinePointerInfo &PtrInfo,
TypeSize Size) {
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 15a2370e5d8b8..85ea45bd5c72f 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -1342,7 +1342,8 @@ class SelectionDAG {
EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment,
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
MachineMemOperand::MOStore,
- LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes());
+ LocationSize Size = LocationSize::precise(0),
+ const AAMDNodes &AAInfo = AAMDNodes());
inline SDValue getMemIntrinsicNode(
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
@@ -1350,7 +1351,8 @@ class SelectionDAG {
MaybeAlign Alignment = std::nullopt,
MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad |
MachineMemOperand::MOStore,
- LocationSize Size = 0, const AAMDNodes &AAInfo = AAMDNodes()) {
+ LocationSize Size = LocationSize::precise(0),
+ const AAMDNodes &AAInfo = AAMDNodes()) {
// Ensure that codegen never sees alignment 0
return getMemIntrinsicNode(Opcode, dl, VTList, Ops, MemVT, PtrInfo,
Alignment.value_or(getEVTAlign(MemVT)), Flags,
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 5086ee8829b25..5b673de8db370 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -2106,7 +2106,7 @@ void BaseMemOpClusterMutation::collectMemOpRecords(
SmallVector<const MachineOperand *, 4> BaseOps;
int64_t Offset;
bool OffsetIsScalable;
- LocationSize Width = 0;
+ LocationSize Width = LocationSize::precise(0);
if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,
OffsetIsScalable, Width, TRI)) {
if (!Width.hasValue())
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 89793c30f3710..8b31bd6799e02 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5298,9 +5298,9 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
MPI = MachinePointerInfo(Info.ptrVal, Info.offset);
else if (Info.fallbackAddressSpace)
MPI = MachinePointerInfo(*Info.fallbackAddressSpace);
- Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs, Ops,
- Info.memVT, MPI, Info.align, Info.flags,
- Info.size, I.getAAMetadata());
+ Result = DAG.getMemIntrinsicNode(
+ Info.opc, getCurSDLoc(), VTs, Ops, Info.memVT, MPI, Info.align,
+ Info.flags, LocationSize::precise(Info.size), I.getAAMetadata());
} else if (!HasChain) {
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
} else if (!I.getType()->isVoidTy()) {
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 7e0a1e2a8a06e..6aaeed39bc81d 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1716,7 +1716,7 @@ bool TargetInstrInfo::getMemOperandWithOffset(
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
SmallVector<const MachineOperand *, 4> BaseOps;
- LocationSize Width = 0;
+ LocationSize Width = LocationSize::precise(0);
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
Width, TRI) ||
BaseOps.size() != 1)
diff --git a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
index 71b937f23cc3c..88ff04d55629c 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
@@ -199,7 +199,7 @@ class SIInsertHardClauses {
int64_t Dummy1;
bool Dummy2;
- LocationSize Dummy3 = 0;
+ LocationSize Dummy3 = LocationSize::precise(0);
SmallVector<const MachineOperand *, 4> BaseOps;
if (Type <= LAST_REAL_HARDCLAUSE_TYPE) {
if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2,
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 4acbc201ec58e..97f69bc9af470 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -382,7 +382,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (DataOpIdx == -1)
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
} else {
// The 2 offset instructions use offset0 and offset1 instead. We can treat
// these as a load with a single offset if the 2 offsets are consecutive.
@@ -418,11 +418,12 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
if (DataOpIdx == -1) {
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
- Width = Width.getValue() + getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(
+ Width.getValue() + TypeSize::getFixed(getOpSize(LdSt, DataOpIdx)));
} else {
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
}
}
return true;
@@ -453,7 +454,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
if (DataOpIdx == -1) // LDS DMA
return false;
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -475,7 +476,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
if (DataOpIdx == -1)
return false; // no return sampler
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -490,7 +491,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
if (DataOpIdx == -1)
return false;
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -509,7 +510,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
if (DataOpIdx == -1) // LDS DMA
return false;
- Width = getOpSize(LdSt, DataOpIdx);
+ Width = LocationSize::precise(getOpSize(LdSt, DataOpIdx));
return true;
}
@@ -3798,7 +3799,8 @@ bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
const MachineInstr &MIb) const {
SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
int64_t Offset0, Offset1;
- LocationSize Dummy0 = 0, Dummy1 = 0;
+ LocationSize Dummy0 = LocationSize::precise(0);
+ LocationSize Dummy1 = LocationSize::precise(0);
bool Offset0IsScalable, Offset1IsScalable;
if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
Dummy0, &RI) ||
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index b80cd2961f1be..64bc5ca134c86 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -3295,11 +3295,11 @@ HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
LocationSize &AccessSize) const {
// Return if it is not a base+offset type instruction or a MemOp.
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
- getAddrMode(MI) != HexagonII::BaseLongOffset &&
- !isMemOp(MI) && !isPostIncrement(MI))
+ getAddrMode(MI) != HexagonII::BaseLongOffset && !isMemOp(MI) &&
+ !isPostIncrement(MI))
return nullptr;
- AccessSize = getMemAccessSize(MI);
+ AccessSize = LocationSize::precise(getMemAccessSize(MI));
unsigned BasePos = 0, OffsetPos = 0;
if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 723a00208ccc0..ecc1b5d2ebe35 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -392,7 +392,7 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
continue;
int64_t Offset0;
- LocationSize Size0 = 0;
+ LocationSize Size0 = LocationSize::precise(0);
MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
// Is the access size is longer than the L1 cache line, skip the check.
if (BaseOp0 == nullptr || !BaseOp0->isReg() || !Size0.hasValue() ||
@@ -406,7 +406,7 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
continue;
int64_t Offset1;
- LocationSize Size1 = 0;
+ LocationSize Size1 = LocationSize::precise(0);
MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
if (BaseOp1 == nullptr || !BaseOp1->isReg() || !Size0.hasValue() ||
Size1.getValue() >= 32 || BaseOp0->getReg() != BaseOp1->getReg())
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 1aeedd531c4ac..4ca97da16cdeb 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -102,7 +102,8 @@ bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
const TargetRegisterInfo *TRI = &getRegisterInfo();
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
int64_t OffsetA = 0, OffsetB = 0;
- LocationSize WidthA = 0, WidthB = 0;
+ LocationSize WidthA = LocationSize::precise(0),
+ WidthB = LocationSize::precise(0);
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
@@ -769,17 +770,17 @@ bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
case Lanai::LDW_RR:
case Lanai::SW_RR:
case Lanai::SW_RI:
- Width = 4;
+ Width = LocationSize::precise(4);
break;
case Lanai::LDHs_RI:
case Lanai::LDHz_RI:
case Lanai::STH_RI:
- Width = 2;
+ Width = LocationSize::precise(2);
break;
case Lanai::LDBs_RI:
case Lanai::LDBz_RI:
case Lanai::STB_RI:
- Width = 1;
+ Width = LocationSize::precise(1);
break;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index f017073911950..ce3b7c9214549 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2926,7 +2926,8 @@ bool PPCInstrInfo::shouldClusterMemOps(
return false;
int64_t Offset1 = 0, Offset2 = 0;
- LocationSize Width1 = 0, Width2 = 0;
+ LocationSize Width1 = LocationSize::precise(0),
+ Width2 = LocationSize::precise(0);
const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
!getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
@@ -5781,7 +5782,8 @@ bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
const TargetRegisterInfo *TRI = &getRegisterInfo();
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
int64_t OffsetA = 0, OffsetB = 0;
- LocationSize WidthA = 0, WidthB = 0;
+ LocationSize WidthA = LocationSize::precise(0),
+ WidthB = LocationSize::precise(0);
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5b5dca4b541df..f13746fc397a6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11375,7 +11375,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
SDValue Chain = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), StoreOps,
ConcatVT.getVectorElementType(), PtrInfo, Alignment,
- MachineMemOperand::MOStore, MemoryLocation::UnknownSize);
+ MachineMemOperand::MOStore, LocationSize::beforeOrAfterPointer());
static const Intrinsic::ID VlsegIntrinsicsIds[] = {
Intrinsic::riscv_vlseg2, Intrinsic::riscv_vlseg3, Intrinsic::riscv_vlseg4,
@@ -11397,7 +11397,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
SDValue Load = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_W_CHAIN, DL, DAG.getVTList({VecTupTy, MVT::Other}),
LoadOps, ConcatVT.getVectorElementType(), PtrInfo, Alignment,
- MachineMemOperand::MOLoad, MemoryLocation::UnknownSize);
+ MachineMemOperand::MOLoad, LocationSize::beforeOrAfterPointer());
SmallVector<SDValue, 8> Res(Factor);
@@ -11514,7 +11514,7 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
SDValue Chain = DAG.getMemIntrinsicNode(
ISD::INTRINSIC_VOID, DL, DAG.getVTList(MVT::Other), Ops,
VecVT.getVectorElementType(), PtrInfo, Alignment,
- MachineMemOperand::MOStore, MemoryLocation::UnknownSize);
+ MachineMemOperand::MOStore, LocationSize::beforeOrAfterPointer());
SmallVector<SDValue, 8> Loads(Factor);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 02f56b7ce5326..83a3ea00d1986 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -3044,7 +3044,8 @@ bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
int64_t OffsetA = 0, OffsetB = 0;
- LocationSize WidthA = 0, WidthB = 0;
+ LocationSize WidthA = LocationSize::precise(0),
+ WidthB = LocationSize::precise(0);
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index d879d99033778..1c2a984b1f62a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4748,8 +4748,8 @@ bool X86InstrInfo::getMemOperandsWithOffsetWidth(
// FIXME: Relying on memoperands() may not be right thing to do here. Check
// with X86 maintainers, and fix it accordingly. For now, it is ok, since
// there is no use of `Width` for X86 back-end at the moment.
- Width =
- !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0;
+ Width = !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize()
+ : LocationSize::precise(0);
BaseOps.push_back(BaseOp);
return true;
}
diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
index f7351f00ae282..3cdc58080aea4 100644
--- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
+++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
@@ -168,7 +168,7 @@ TEST_P(RISCVInstrInfoTest, GetMemOperandsWithOffsetWidth) {
DebugLoc DL;
SmallVector<const MachineOperand *> BaseOps;
- LocationSize Width = 0;
+ LocationSize Width = LocationSize::precise(0);
int64_t Offset;
bool OffsetIsScalable;
>From 4bbcf54eb5a490ce7f4b07b91e5eeab8d04921e0 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Thu, 27 Mar 2025 20:56:40 -0700
Subject: [PATCH 2/2] Address review comment
---
llvm/include/llvm/Analysis/MemoryLocation.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h
index 345dbe0cf0e50..67e98e3daa416 100644
--- a/llvm/include/llvm/Analysis/MemoryLocation.h
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h
@@ -192,13 +192,13 @@ class LocationSize {
bool operator==(const TypeSize &Other) const {
return (*this == LocationSize::precise(Other));
}
- bool operator==(const uint64_t &Other) const {
+ bool operator==(uint64_t Other) const {
return (*this == LocationSize::precise(Other));
}
bool operator!=(const LocationSize &Other) const { return !(*this == Other); }
bool operator!=(const TypeSize &Other) const { return !(*this == Other); }
- bool operator!=(const uint64_t &Other) const { return !(*this == Other); }
+ bool operator!=(uint64_t Other) const { return !(*this == Other); }
// Ordering operators are not provided, since it's unclear if there's only one
// reasonable way to compare:
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