[llvm] [AMDGPU] Simplify 2 fp8 conversion profiles. NFC. (PR #133328)
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 27 15:11:13 PDT 2025
https://github.com/rampitec created https://github.com/llvm/llvm-project/pull/133328
None
>From 593c1e1e7d97a2ba21b4db6f8a1b7e9cc43fd990 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: Thu, 27 Mar 2025 15:10:31 -0700
Subject: [PATCH] [AMDGPU] Simplify 2 fp8 conversion profiles. NFC.
---
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 37 ++++++++--------------
1 file changed, 13 insertions(+), 24 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index a03a6f61ce0cb..41ad509f11c60 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -220,7 +220,7 @@ defm V_ALIGNBIT_B32 : VOP3Inst_t16_with_profiles <"v_alignbit_b32",
defm V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
let True16Predicate = UseRealTrue16Insts in
defm V_ALIGNBYTE_B32_t16 : VOP3Inst <"v_alignbyte_b32_t16", VOP3_Profile_True16<VOP_I32_I32_I32_I16, VOP3_OPSEL>>;
-let True16Predicate = UseFakeTrue16Insts in
+let True16Predicate = UseFakeTrue16Insts in
defm V_ALIGNBYTE_B32_fake16 : VOP3Inst <"v_alignbyte_b32_fake16", VOP3_Profile_Fake16<VOP_I32_I32_I32_I16, VOP3_OPSEL>>;
// XXX - No FPException seems suspect but manual doesn't say it does
@@ -556,27 +556,16 @@ def shl_0_to_4 : PatFrag<
}
def VOP3_CVT_PK_F8_F32_Profile : VOP3_Profile<VOP_I32_F32_F32, VOP3_OPSEL> {
- let InsVOP3OpSel = (ins FP32InputMods:$src0_modifiers, Src0RC64:$src0,
- FP32InputMods:$src1_modifiers, Src1RC64:$src1,
- VGPR_32:$vdst_in, op_sel0:$op_sel);
- let InsVOP3DPP = (ins VGPR_32:$old,
- FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
- FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
- VGPR_32:$vdst_in, op_sel0:$op_sel,
- dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
- DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl);
-
- let InsVOP3DPP16 = (ins VGPR_32:$old,
- FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
- FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
- VGPR_32:$vdst_in, op_sel0:$op_sel,
- dpp_ctrl:$dpp_ctrl, DppRowMask:$row_mask,
- DppBankMask:$bank_mask, DppBoundCtrl:$bound_ctrl, Dpp16FI:$fi);
- let InsVOP3DPP8 = (ins VGPR_32:$old,
- FP32InputMods:$src0_modifiers, Src0VOP3DPP:$src0,
- FP32InputMods:$src1_modifiers, Src1VOP3DPP:$src1,
- VGPR_32:$vdst_in, op_sel0:$op_sel, dpp8:$dpp8, Dpp8FI:$fi);
-
+ defvar Tail = (ins VGPR_32:$vdst_in, op_sel0:$op_sel);
+ let InsVOP3OpSel = !con(getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
+ 0, HasModifiers, HasSrc2Mods,
+ HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret,
+ Tail);
+ let InsVOP3Base = !con(getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP,
+ Src2VOP3DPP, NumSrcArgs, 0, HasModifiers,
+ HasSrc2Mods, HasOMod, Src0ModVOP3DPP, Src1ModVOP3DPP,
+ Src2ModVOP3DPP, false>.ret,
+ Tail);
let HasClamp = 0;
let HasExtVOP3DPP = 1;
}
@@ -621,12 +610,12 @@ class VOP3_CVT_SR_F8_ByteSel_Profile<ValueType SrcVT> :
let HasClamp = 0;
defvar bytesel = (ins VGPR_32:$vdst_in, ByteSel:$byte_sel);
let Ins64 = !con(getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
- HasClamp, HasModifiers, HasSrc2Mods,
+ 0, HasModifiers, HasSrc2Mods,
HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret,
bytesel);
let InsVOP3Base = !con(
getInsVOP3Base<Src0VOP3DPP, Src1VOP3DPP,
- Src2VOP3DPP, NumSrcArgs, HasClamp, HasModifiers, HasSrc2Mods, HasOMod,
+ Src2VOP3DPP, NumSrcArgs, 0, HasModifiers, HasSrc2Mods, HasOMod,
Src0ModVOP3DPP, Src1ModVOP3DPP, Src2ModVOP3DPP, HasOpSel>.ret,
bytesel);
}
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