[llvm] Add RISC-V support information to readme (PR #132699)

[via llvm-commits]

================
@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISC-V
+  * RV64I/E, RV32I/E and extensions supported by LLVM's RISC-V backend with some limitations.
----------------
AnastasiyaChernikova wrote:

Addressed

https://github.com/llvm/llvm-project/pull/132699