[llvm] [BOLT][AArch64] Partial support for lite mode (PR #133014)

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff b0668d859b237f6991f416b688cedb7389354fd8 ccba2de4295f7d3b4bd9b7af62d0d10957c077ba --extensions h,cpp -- bolt/include/bolt/Core/BinaryContext.h bolt/include/bolt/Core/BinaryFunction.h bolt/lib/Core/BinaryContext.cpp bolt/lib/Core/BinaryFunction.cpp bolt/lib/Passes/BinaryPasses.cpp bolt/lib/Rewrite/RewriteInstance.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp
index 5ee33f52ec..33c752e4e7 100644
--- a/bolt/lib/Core/BinaryFunction.cpp
+++ b/bolt/lib/Core/BinaryFunction.cpp
@@ -1695,7 +1695,7 @@ bool BinaryFunction::scanExternalRefs() {
     // Linker relaxation is documented at:
     // https://github.com/ARM-software/abi-aa/blob/main/aaelf64/aaelf64.rst
     // under #relocation-optimization.
-    if (const Relocation *Rel;
+    if (const Relocation * Rel;
         BC.isAArch64() && (Rel = getRelocationAt(Offset))) {
       // NOP+ADR sequence can originate from either ADRP+ADD or ADRP+LDR.
       // In either case, we convert it into ADRP+ADD.

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https://github.com/llvm/llvm-project/pull/133014