[llvm] Add RISC-V support information to readme (PR #132699)

[Aiden Grossman via llvm-commits]

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@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISC-V
+  * RV64I/E, RV32I/E and extensions supported by LLVM's RISC-V backend with some limitations.
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boomanaiden154 wrote:

Same here.

https://github.com/llvm/llvm-project/pull/132699