[llvm] 0ae6185 - [RISCV] Manually update MIR inputs to reflect #79e82b6
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 27 08:33:08 PDT 2025
Author: Philip Reames
Date: 2025-03-27T08:32:53-07:00
New Revision: 0ae6185b455876b98cf58888117e3043cb43d060
URL: https://github.com/llvm/llvm-project/commit/0ae6185b455876b98cf58888117e3043cb43d060
DIFF: https://github.com/llvm/llvm-project/commit/0ae6185b455876b98cf58888117e3043cb43d060.diff
LOG: [RISCV] Manually update MIR inputs to reflect #79e82b6
Since we've changed what get's generated, we should update the snapshots
of MIR. Otherwise, we end up testing configurations which are no longer
possible from codegen.
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
index f7c364f0f6f1a..c728fcb8d8b0d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
@@ -15,7 +15,7 @@
; CHECK-NEXT: vsetivli a5, 1, e16, m1, ta, mu
; CHECK-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi a1, sp, 24
- ; CHECK-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill
+ ; CHECK-NEXT: vs1r.v v25, (a1) # vscale x 8-byte Folded Spill
; CHECK-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: call fixedlen_vector_spillslot
; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
@@ -48,7 +48,7 @@ body: |
SD $x10, %stack.0, 0
SD $x10, %stack.2, 0
dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
- VS1R_V killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8)
+ VS1R_V killed renamable $v25, %stack.1 :: (store (<vscale x 1 x s64>) into %stack.1, align 8)
; This is here just to make all the eligible registers live at this point.
; This way when we replace the frame index %stack.1 with its actual address
; we have to allocate a virtual register to compute it.
diff --git a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
index 41b3bcdc5be5a..89f4950366468 100644
--- a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
@@ -30,7 +30,7 @@
; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi a0, sp, 2047
; CHECK-NEXT: addi a0, a0, 241
- ; CHECK-NEXT: vs1r.v v25, (a0) # Unknown-size Folded Spill
+ ; CHECK-NEXT: vs1r.v v25, (a0) # vscale x 8-byte Folded Spill
; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: call spillslot
; CHECK-NEXT: addi sp, s0, -2032
@@ -82,7 +82,7 @@ body: |
bb.0:
liveins: $x1, $x5, $x6, $x7, $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $x28, $x29, $x30, $x31, $v25
- VS1R_V killed renamable $v25, %stack.1 :: (store unknown-size into %stack.1, align 8)
+ VS1R_V killed renamable $v25, %stack.1 :: (store (<vscale x 1 x s64>) into %stack.1, align 8)
; This is here just to make all the eligible registers live at this point.
; This way when we replace the frame index %stack.1 with its actual address
; we have to allocate two virtual registers to compute it.
diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
index 268e21b0732ab..e3f2a4313630d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir
@@ -16,7 +16,7 @@
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: addi a0, sp, 16
- ; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill
+ ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -41,7 +41,7 @@
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; CHECK-NEXT: addi a0, sp, 64
- ; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill
+ ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill
; CHECK-NEXT: addi sp, s0, -80
; CHECK-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
@@ -69,7 +69,7 @@ body: |
$x25 = COPY $x10
SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
- VS2R_V renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+ VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)
PseudoRET
...
@@ -88,7 +88,7 @@ body: |
$x25 = COPY $x10
SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
- VS2R_V renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+ VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)
PseudoRET
...
diff --git a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
index 07e7ad5184f08..a78691557b643 100644
--- a/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv64.mir
@@ -16,7 +16,7 @@
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi a0, sp, 32
- ; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill
+ ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
@@ -45,7 +45,7 @@ body: |
$x25 = COPY $x10
SD renamable $x25, %stack.0, 0 :: (store (s64) into %stack.0)
- VS2R_V renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+ VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)
PseudoRET
...
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
index 2b1ed7df010e0..715765c3006f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
@@ -70,8 +70,8 @@ body: |
%0:gpr = COPY $x10
%1:gprnox0 = COPY $x11
$v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, %0, %1, 6, 0
- PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0 :: (store unknown-size into %stack.0, align 8)
- renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 %stack.0 :: (load unknown-size from %stack.0, align 8)
+ PseudoVSPILL7_M1 killed renamable $v0_v1_v2_v3_v4_v5_v6, %stack.0 :: (store (<vscale x 7 x s64>) into %stack.0, align 8)
+ renamable $v7_v8_v9_v10_v11_v12_v13 = PseudoVRELOAD7_M1 %stack.0 :: (load (<vscale x 7 x s64>) from %stack.0, align 8)
VS1R_V killed $v8, %0:gpr
PseudoRET
...
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