[llvm] [AMDGPU][True16][CodeGen] srl pattern for true16 mode (PR #132987)

[Brox Chen via llvm-commits]

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@@ -2425,6 +2425,13 @@ def : GCNPat <(i1 imm:$imm),
   let WaveSizePredicate = isWave32;
 }
 
+let True16Predicate = UseRealTrue16Insts in
+foreach vt = [i32, v2i16] in
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broxigarchen wrote:

I might misunderstood srl on vector type. Let me try something and I will address this in the follow up patch

https://github.com/llvm/llvm-project/pull/132987