[llvm] [AMDGPU][True16][CodeGen] srl pattern for true16 mode (PR #132987)

[Brox Chen via llvm-commits]

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@@ -2425,6 +2425,13 @@ def : GCNPat <(i1 imm:$imm),
   let WaveSizePredicate = isWave32;
 }
 
+let True16Predicate = UseRealTrue16Insts in
+foreach vt = [i32, v2i16] in
+def : GCNPat <
+  (vt (DivergentBinFrag<srl> VGPR_32:$src, (i32 16))),
+  (REG_SEQUENCE VGPR_32, (i16 (EXTRACT_SUBREG $src, hi16)), lo16, (V_MOV_B16_t16_e64 0, (i16 0x0000), 0), hi16)
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broxigarchen wrote:

Hi Matt. Thanks for the review. I checked the performSrlCombine function. I think it's currently checking for 64bit SRL with a dynamic right shift bits, which probably cannot be put in a isel pattern.

I think for this case since the right shift bit is a constant 16, it's probably better to directly place it in the isel pattern. (If I understand correctly we prefer isel pattern better than customization in the pass)

https://github.com/llvm/llvm-project/pull/132987