[llvm] b38c23b - [RISCV] Update two autogen tests to reduce spurious diffs [NFC]

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2025-03-27T08:00:40-07:00
New Revision: b38c23b4c199221af9e043041f2e594ec1e3745b

URL: https://github.com/llvm/llvm-project/commit/b38c23b4c199221af9e043041f2e594ec1e3745b
DIFF: https://github.com/llvm/llvm-project/commit/b38c23b4c199221af9e043041f2e594ec1e3745b.diff

LOG: [RISCV] Update two autogen tests to reduce spurious diffs [NFC]

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
    llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
index 0cf2486308c4e..f7c364f0f6f1a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
@@ -1,5 +1,4 @@
 # NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# NOTE: Assertions gave been autogenerated by utils/update_llc_test_checks.py
 # RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \
 # RUN:     -verify-machineinstrs %s | FileCheck %s
 --- |
@@ -14,10 +13,10 @@
   ; CHECK-NEXT:    sd a0, 32(sp)
   ; CHECK-NEXT:    sd a0, 16(sp)
   ; CHECK-NEXT:    vsetivli a5, 1, e16, m1, ta, mu
-  ; CHECK-NEXT:    sd a1, 0(sp)
+  ; CHECK-NEXT:    sd a1, 0(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    addi a1, sp, 24
   ; CHECK-NEXT:    vs1r.v v25, (a1) # Unknown-size Folded Spill
-  ; CHECK-NEXT:    ld a1, 0(sp)
+  ; CHECK-NEXT:    ld a1, 0(sp) # 8-byte Folded Reload
   ; CHECK-NEXT:    call fixedlen_vector_spillslot
   ; CHECK-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
   ; CHECK-NEXT:    addi sp, sp, 48

diff  --git a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
index 559362e6d6274..41b3bcdc5be5a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
@@ -17,21 +17,21 @@
   ; CHECK-NEXT:    addi s0, sp, 2032
   ; CHECK-NEXT:    .cfi_def_cfa s0, 0
   ; CHECK-NEXT:    addi sp, sp, -272
-  ; CHECK-NEXT:    sd a0, 8(sp)
+  ; CHECK-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    csrr a0, vlenb
-  ; CHECK-NEXT:    sd a1, 0(sp)
+  ; CHECK-NEXT:    sd a1, 0(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    li a1, 3
   ; CHECK-NEXT:    slli a1, a1, 10
   ; CHECK-NEXT:    mul a0, a0, a1
-  ; CHECK-NEXT:    ld a1, 0(sp)
+  ; CHECK-NEXT:    ld a1, 0(sp) # 8-byte Folded Reload
   ; CHECK-NEXT:    sub sp, sp, a0
-  ; CHECK-NEXT:    ld a0, 8(sp)
+  ; CHECK-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
   ; CHECK-NEXT:    andi sp, sp, -128
-  ; CHECK-NEXT:    sd a0, 8(sp)
+  ; CHECK-NEXT:    sd a0, 8(sp) # 8-byte Folded Spill
   ; CHECK-NEXT:    addi a0, sp, 2047
   ; CHECK-NEXT:    addi a0, a0, 241
   ; CHECK-NEXT:    vs1r.v v25, (a0) # Unknown-size Folded Spill
-  ; CHECK-NEXT:    ld a0, 8(sp)
+  ; CHECK-NEXT:    ld a0, 8(sp) # 8-byte Folded Reload
   ; CHECK-NEXT:    call spillslot
   ; CHECK-NEXT:    addi sp, s0, -2032
   ; CHECK-NEXT:    .cfi_def_cfa sp, 2032