[llvm] a6e5616 - [RISCV] Modify operand regclass in load store patterns (#133071)

[via llvm-commits]

Author: Sudharsan Veeravalli
Date: 2025-03-27T17:20:25+05:30
New Revision: a6e56162c251db180f4618202c8088acba311ce8

URL: https://github.com/llvm/llvm-project/commit/a6e56162c251db180f4618202c8088acba311ce8
DIFF: https://github.com/llvm/llvm-project/commit/a6e56162c251db180f4618202c8088acba311ce8.diff

LOG: [RISCV] Modify operand regclass in load store patterns (#133071)

$rs1 is defined as GPRMem in the correspoding instruction definition
classes.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 253f24aa0d68d..b61992298ca95 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1836,8 +1836,8 @@ def PseudoZEXT_W : Pseudo<(outs GPR:$rd), (ins GPR:$rs), [], "zext.w", "$rd, $rs
 /// Loads
 
 class LdPat<PatFrag LoadOp, RVInst Inst, ValueType vt = XLenVT>
-    : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
-          (Inst GPR:$rs1, simm12:$imm12)>;
+    : Pat<(vt (LoadOp (AddrRegImm (XLenVT GPRMem:$rs1), simm12:$imm12))),
+          (Inst GPRMem:$rs1, simm12:$imm12)>;
 
 def : LdPat<sextloadi8, LB>;
 def : LdPat<extloadi8, LBU>; // Prefer unsigned due to no c.lb in Zcb.
@@ -1851,9 +1851,9 @@ def : LdPat<zextloadi16, LHU>;
 
 class StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy,
             ValueType vt>
-    : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPR:$rs1),
+    : Pat<(StoreOp (vt StTy:$rs2), (AddrRegImm (XLenVT GPRMem:$rs1),
                    simm12:$imm12)),
-          (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
+          (Inst StTy:$rs2, GPRMem:$rs1, simm12:$imm12)>;
 
 def : StPat<truncstorei8, SB, GPR, XLenVT>;
 def : StPat<truncstorei16, SH, GPR, XLenVT>;