[llvm] 1a14082 - [RISCV] Have GPRMem on the correct operand in QCIRVInstESStore (#133042)

[via llvm-commits]

Author: Sudharsan Veeravalli
Date: 2025-03-27T17:02:32+05:30
New Revision: 1a140820ab6962a387eeec17ebe669c724822c49

URL: https://github.com/llvm/llvm-project/commit/1a140820ab6962a387eeec17ebe669c724822c49
DIFF: https://github.com/llvm/llvm-project/commit/1a140820ab6962a387eeec17ebe669c724822c49.diff

LOG: [RISCV] Have GPRMem on the correct operand in QCIRVInstESStore (#133042)

It should be on rs1 and not rs2.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 69290c0da1824..86c521010add4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -442,7 +442,7 @@ class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
     : QCIRVInstESBase<funct3, funct2, (outs),
-                      (ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
+                      (ins GPR:$rs2, GPRMem:$rs1, simm26:$imm),
                       opcodestr, "$rs2, ${imm}(${rs1})">;
 
 class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>